Patents by Inventor Ullas Singh
Ullas Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097692Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Applicant: Avago Technologies International Sales Pte. LimitedInventors: Ullas Singh, Namik Kocaman, Mohammadamin Torabi, Meisam Honarvar Nazari, Mehmet Batuhan Dayanik, Delong Cui, Jun Cao
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Patent number: 11863198Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.Type: GrantFiled: March 21, 2022Date of Patent: January 2, 2024Assignee: Avago Technologies International Sales Pte. LimitedInventors: Ullas Singh, Namik Kocaman, Mohammadamin Torabi, Meisam Honarvar Nazari, Mehmet Batuhan Dayanik, Delong Cui, Jun Cao
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Publication number: 20230299781Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Inventors: Ullas Singh, Namik Kocaman, Mohammadamin Torabi, Meisam Honarvar Nazari, Mehmet Batuhan Dayanik, Delong Cui, Jun Cao
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Publication number: 20230299785Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Inventors: Ullas Singh, Namik Kocaman, Mohammadamin Torabi, Meisam Honarvar Nazari, Mehmet Batuhan Dayanik, Delong Cui, Jun Cao
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Patent number: 10749714Abstract: Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal.Type: GrantFiled: December 28, 2018Date of Patent: August 18, 2020Assignee: Avago Technologies International Sales Pte. LimitedInventors: Arvindh Iyer, Kumar Thasari, Bo Zhang, Heng Zhang, Jaehun Jeong, Ullas Singh, Namik Kocaman
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Publication number: 20200213165Abstract: Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Arvindh IYER, Kumar THASARI, Bo ZHANG, Heng ZHANG, Jaehun JEONG, Ullas SINGH, Namik KOCAMAN
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Patent number: 10505767Abstract: Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal.Type: GrantFiled: December 28, 2018Date of Patent: December 10, 2019Assignee: Avago Technologies International Sales Pte. LimitedInventors: Heng Zhang, Jaehun Jeong, Bo Zhang, Arvindh Iyer, Kumar Thasari, Ullas Singh, Namik Kocaman
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Patent number: 10389377Abstract: A keeper based switch driver can generate overlapping differential signals and increase a crossing point of the overlapping differential signals a first predetermined amount. Additionally, the keeper based switch driver can further increase the crossing point of the overlapping differential signals a second predetermined amount and limit signal swing to an absolute value of a drain-source voltage. A microprocessor can also be electrically connected to a DAC cell with keeper based switch driver through a performance detection circuit. The microprocessor can be configured to receive information from a performance detection circuit and control a current of a variable current source in a keeper bias circuit accordingly.Type: GrantFiled: December 17, 2018Date of Patent: August 20, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Kumar Thasari, Ullas Singh, Arvindh Iyer, Namik Kocaman
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Publication number: 20190189734Abstract: Systems and methods disclosed herein provide a coupled T-coil circuit for differential mode bandwidth extension and common mode rejection. The coupled T-coil circuit includes a first layer including at least a first portion of a first T-coil circuit and a first portion of a second T-coil circuit, and a second layer disposed on top of the first layer and interconnected to the first layer, the second layer including at least a second portion of the first T-coil circuit and a second portion of the second T-coil circuit. The first T-coil circuit includes one or more first coils with a first wind direction. The second T-coil circuit comprises one or more second coils with a second wind direction. The first wind direction can be opposite the second wind direction.Type: ApplicationFiled: December 20, 2017Publication date: June 20, 2019Inventors: Guansheng Li, Ullas Singh, Delong Cui, Jun Cao, Afshin Momtaz
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Patent number: 10187080Abstract: A keeper based switch driver can generate overlapping differential signals and increase a crossing point of the overlapping differential signals a first predetermined amount. Additionally, the keeper based switch driver can further increase the crossing point of the overlapping differential signals a second predetermined amount and limit signal swing to an absolute value of a drain-source voltage. A microprocessor can also be electrically connected to a DAC cell with keeper based switch driver through a performance detection circuit. The microprocessor can be configured to receive information from a performance detection circuit and control a current of a variable current source in a keeper bias circuit accordingly.Type: GrantFiled: April 26, 2018Date of Patent: January 22, 2019Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventors: Kumar Thasari, Ullas Singh, Arvindh Iyer, Namik Kocaman
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Patent number: 9325316Abstract: A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.Type: GrantFiled: May 11, 2015Date of Patent: April 26, 2016Assignee: Broadcom CorporationInventors: Amr Amin Hafez Amin Abou-El-Sonoun, Ramy Awad, Mohammed Abdul-Latif, Adesh Garg, Henry Park, Anand Jitendra Vasani, Ullas Singh, Namik Kemal Kocaman, Afshin Momtaz
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Patent number: 8618835Abstract: An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.Type: GrantFiled: September 23, 2011Date of Patent: December 31, 2013Assignee: Broadcom CorporationInventors: Burak Catli, Ali Nazemi, Mahmoud Reza Ahmadi, Ullas Singh, Jun Cao, Afshin Momtaz
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Publication number: 20130076394Abstract: An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.Type: ApplicationFiled: September 23, 2011Publication date: March 28, 2013Applicant: Broadcom CorporationInventors: Burak Catli, Ali Nazemi, Mahmoud Reza Ahmadi, Ullas Singh, Jun Cao, Afshin Momtaz
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Patent number: 8170150Abstract: Digitally controlled phase interpolator circuit. A phase selection control word undergoes decoding to generate a switch control word. The phase selection control word includes 2 quadrant indicating bits and phase interpolating bits for a 4 clock scheme (e.g., 4 clocks having phases 0°, 90°, 180°, and 270°). Such a phase selection control word could includes 3 sector indicating bits and phase interpolating bits for an 8 clock scheme (e.g., 8 clocks having phases 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). The gates of a number of differential pairs of transistors receive the various clock signals. A number of switching circuits direct current from corresponding current sources/supplies to coupled sources of the differential pairs of transistors, and an output clock is taken from coupled drains of the differential pairs of transistors. One or more current sources/supplies can be implemented to provide continuous current (e.g., in an always on manner) to the differential pairs of transistors.Type: GrantFiled: March 21, 2008Date of Patent: May 1, 2012Assignee: Broadcom CorporationInventor: Ullas Singh
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Publication number: 20090238307Abstract: Digitally controlled phase interpolator circuit. A phase selection control word undergoes decoding to generate a switch control word. The phase selection control word includes 2 quadrant indicating bits and phase interpolating bits for a 4 clock scheme (e.g., 4 clocks having phases 0°, 90°, 180°, and 270°). Such a phase selection control word could includes 3 sector indicating bits and phase interpolating bits for an 8 clock scheme (e.g., 8 clocks having phases 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). The gates of a number of differential pairs of transistors receive the various clock signals. A number of switching circuits direct current from corresponding current sources/supplies to coupled sources of the differential pairs of transistors, and an output clock is taken from coupled drains of the differential pairs of transistors. One or more current sources/supplies can be implemented to provide continuous current (e.g., in an always on manner) to the differential pairs of transistors.Type: ApplicationFiled: March 21, 2008Publication date: September 24, 2009Applicant: Broadcom CorporationInventor: Ullas Singh