Abstract: Some embodiments of the invention relate to a sense amplifier configured to determine the slope of a bitline charging voltage and to utilize the determined slope in combination with a voltage level sensing scheme to aid in reading data from a memory cell associated with the bitline. In particular, a sense amplifier circuit is configured to determine a slope of a bit line charging voltage and based upon the determined slope to adjust the slope of the bitline voltage (e.g., by adding a dynamic slope dependent current to a memory cell current configured to charge the bitline) provided to a sense amplifier. By adjusting the slope of the bitline voltage, the charging speed of memory cells in a low resistive state (e.g., having a high cell current and therefore a good SNR) can be increased.

Abstract: An electronic device provides a stack of semiconductor chips. A redistribution layer of a first semiconductor chip is arranged at the bottom of the stack. The redistribution layer of the first semiconductor chip comprises external pads.

Abstract: Some embodiments of the invention relate to a sense amplifier configured to determine the slope of a bitline charging voltage and to utilize the determined slope in combination with a voltage level sensing scheme to aid in reading data from a memory cell associated with the bitline. In particular, a sense amplifier circuit is configured to determine a slope of a bit line charging voltage and based upon the determined slope to adjust the slope of the bitline voltage (e.g., by adding a dynamic slope dependent current to a memory cell current configured to charge the bitline) provided to a sense amplifier. By adjusting the slope of the bitline voltage, the charging speed of memory cells in a low resistive state (e.g., having a high cell current and therefore a good SNR) can be increased.

Abstract: A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.

Abstract: A memory die, including a memory array, a memory array data terminal and a data bus that includes a first sub bus and a second sub bus is disclosed. A first bi-directional buffer arranged between the memory array data terminal and the first sub bus and a second bi-directional buffer arranged between the memory array data terminal and the second sub bus is also disclosed. The first and second bi-directional buffers are adapted to couple the first sub bus or the second sub bus to the memory array data terminal at a time.

Abstract: An electronic device provides a stack of semiconductor chips. A redistribution layer of a first semiconductor chip is arranged at the bottom of the stack. The redistribution layer of the first semiconductor chip comprises external pads.

Abstract: The invention relates to an input circuit for an electronic circuit, for receiving and assessing an input signal and for driving the input signal to a downstream circuit. The input circuit includes a first reception circuit which is configured to receive and drive the input signal and has a first current consumption characteristic, the current consumption of the first reception circuit depending on the input signal to be driven, a second reception circuit which is configured to receive and drive the input signal and has a second current consumption characteristic, the current consumption of the second reception circuit depending on the input signal to be driven, wherein the first reception circuit and the second reception circuit may be activated separately, and a control circuit configured to activate either the first reception circuit or the second reception circuit and to deactivate the respective other reception circuit on the basis of the driven input signal.

Abstract: The invention creates an electronic circuit arrangement for receiving a received electrical signal (101) with a first receiving device (100), a second receiving device (200) and a comparator unit (301) for comparing a second signal difference (207), output by the second receiving device (200), with a target value signal (303) and for outputting a control signal (305) in dependence on the comparison, wherein the control signal (305) controls both the first receiving device (100) and the second receiving device (200) into a respective operating point in such a manner that the amplified second signal difference (207) is held at a level of the target value signal (303) and a first signal difference (107) output from the first receiving device (100) supplies with high accuracy a measure of the received signal (101) with respect to a predetermined reference signal (103).

Abstract: A digital memory circuit has at least two pairs of adjacent memory banks. Each of the banks has n parallel terminals for n read/write data lines. Each bank pair has only two bundles of n/2 read/write data lines. A first bundle is assigned to the first half of a first bank and to a second half of a second bank and the second bundle is assigned to a second half of the first bank and to a first half of the second bank. Data are input/output in parallel to n/2 input/output lines with the timing of successive half-periods of a clock signal. A changeover device is changeable between different switching states for connecting a bundle of n/2 input/output lines to the read/write data lines of the bank pair containing the addressed bank, depending on whether the data are assigned to the first or second half-period of the clock signal.

Abstract: A differential amplifier circuit has two input transistors, a load element, and a current source. A terminal for an input voltage is connected to a control terminal of a first input transistor. A terminal for a reference voltage is connected to a control terminal of a second input transistor. The two input transistors are connected in parallel between the load element and a terminal of the current source. A terminal for an internal reference potential is connected to a further terminal of the current source. A regulating circuit, is connected to the terminal for the voltage and to the terminal for the reference potential, and regulates the potential of the circuit dependent on changes in the reference voltage. Fluctuations of the reference voltage are compensated by regulation of the internal reference potential. As a result, the operating point of the circuit is stabilized independently of fluctuations of the reference voltage.

Abstract: The invention relates to an input circuit for an electronic circuit, for receiving and assessing an input signal and for driving the input signal to a downstream circuit. The input circuit includes a first reception circuit which is configured to receive and drive the input signal and has a first current consumption characteristic, the current consumption of the first reception circuit depending on the input signal to be driven, a second reception circuit which is configured to receive and drive the input signal and has a second current consumption characteristic, the current consumption of the second reception circuit depending on the input signal to be driven, wherein the first reception circuit and the second reception circuit may be activated separately, and a control circuit configured to activate either the first reception circuit or the second reception circuit and to deactivate the respective other reception circuit on the basis of the driven input signal.

Abstract: An RC network is integrated in a semiconductor circuit chip and is connected between an input pad or pin and a ground node coupled to a substrate of the chip. The RC network has a plurality of resistance elements, a plurality of capacitance elements and a plurality of connection/isolation elements, which are provided in each case between at least one of the resistance elements and the individual capacitive elements. The inventive circuit configuration enables an optional and independent setting of the input capacitance and of the input resistance of the semiconductor circuit chip, depending on the connection/isolation state of the connection/isolation elements.

Abstract: A differential amplifier circuit has two input transistors, a load element, and a current source. A terminal for an input voltage is connected to a control terminal of a first input transistor. A terminal for a reference voltage is connected to a control terminal of a second input transistor. The two input transistors are connected in parallel between the load element and a terminal of the current source. A terminal for an internal reference potential is connected to a further terminal of the current source. A regulating circuit, is connected to the terminal for the voltage and to the terminal for the reference potential, and regulates the potential of the circuit dependent on changes in the reference voltage. Fluctuations of the reference voltage are compensated by regulation of the internal reference potential. As a result, the operating point of the circuit is stabilized independently of fluctuations of the reference voltage.

Abstract: In order to achieve an optimally stable synchronization of clock signals, a temperature-controlled delay device with which it is possible to generate a signal delay that is dependent on operating temperature is provided in a synchronization device for a semiconductor memory device. In this manner, the clock signal can be time-tuned in a particular reliable fashion.

Abstract: A digital memory circuit has at least two pairs of adjacent memory banks. Each of the banks has n parallel terminals for n read/write data lines. Each bank pair has only two bundles of n/2 read/write data lines. A first bundle is assigned to the first half of a first bank and to a second half of a second bank and the second bundle is assigned to a second half of the first bank and to a first half of the second bank. Data are input/output in parallel to n/2 input/output lines with the timing of successive half-periods of a clock signal. A changeover device is changeable between different switching states for connecting a bundle of n/2 input/output lines to the read/write data lines of the bank pair containing the addressed bank, depending on whether the data are assigned to the first or second half-period of the clock signal.

Abstract: In order to achieve an optimally stable synchronization of clock signals, a temperature-controlled delay device with which it is possible to generate a signal delay that is dependent on an operating temperature is provided in a synchronization device for a semiconductor memory device. In this manner, the clock signal can be time-tuned in a particularly reliable fashion.

Abstract: An RC network is integrated in a semiconductor circuit chip and is connected between an input pad or pin and a ground node coupled to a substrate of the chip. The RC network has a plurality of resistance elements, a plurality of capacitance elements and a plurality of connection/isolation elements, which are provided in each case between at least one of the resistance elements and the individual capacitive elements. The inventive circuit configuration enables an optional and independent setting of the input capacitance and of the input resistance of the semiconductor circuit chip, depending on the connection/isolation state of the connection/isolation elements.

Abstract: A circuit configuration for enabling a clock signal in a manner dependent on an enable signal has first and second signal paths that are fed to a NAND gate. The second signal path contains an RS flip-flop, upstream of which NAND gates are connected, which, for their part, are connected via different inverters to the input terminals for the clock signal and the enable signal, respectively.

Abstract: A circuit configuration for enabling a clock signal in a manner dependent on an enable signal has first and second signal paths that are fed to a NAND gate. The second signal path contains an RS flip-flop, upstream of which NAND gates are connected, which, for their part, are connected via different inverters to the input terminals for the clock signal and the enable signal, respectively.