Abstract: A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a system for defining variable patterns using a pattern description language to create a glyph layout; and a graph-based pattern matching system that can identify potential matches amongst variable patterns in the glyph layout.

Abstract: A system and method for processing glyph-based data associated with generating very large scale integrated circuit (VLSI) designs. A system is provide that includes a serialization system for converting an input region of glyph design data into a pseudo-string; and a pattern searching system that identifies matching patterns in the glyph design data by analyzing pseudo-strings generated by the serialization system. Pattern searching may include, e.g., predefined pattern searching and redundant pattern searching.

Abstract: An apparatus for serializing concurrent requests to multiple processors includes a signal merging tree structure and a traversal mechanism. The tree structure has a root node and leaf nodes for connecting a data consumer to the root. The tree structure serializes concurrent requests in the presence of race conditions, and connects each request producer from among the processors to a respective leaf node. The mechanism enables a producer to transmit a signal from a corresponding leaf node to the consumer at the root node by setting all nodes on a path from the leaf node to the root node to a Boolean true. The mechanism enables the consumer to trace signal submissions of the producers such that submission traversals by the producers and trace traversals by the consumer can be concurrently performed to allow data races between signal submissions by producers and between signal submissions by producers and the consumer.

Abstract: An apparatus for serializing concurrent requests to multiple processors includes a signal merging tree structure and a traversal mechanism. The tree structure has a root node and leaf nodes for connecting a data consumer to the root. The tree structure serializes concurrent requests in the presence of race conditions, and connects each request producer from among the processors to a respective leaf node. The mechanism enables a producer to transmit a signal from a corresponding leaf node to the consumer at the root node by setting all nodes on a path from the leaf node to the root node to a Boolean true. The mechanism enables the consumer to trace signal submissions of the producers such that submission traversals by the producers and trace traversals by the consumer can be concurrently performed to allow data races between signal submissions by producers and between signal submissions by producers and the consumer.

Abstract: An apparatus for serializing concurrent requests to multiple processors includes a signal merging tree structure and a traversal mechanism. The tree structure has a root node and leaf nodes for connecting a data consumer to the root. The tree structure serializes concurrent requests in the presence of race conditions, and connects each request producer from among the processors to a respective leaf node. The mechanism enables a producer to transmit a signal from a corresponding leaf node to the consumer at the root node by setting all nodes on a path from the leaf node to the root node to a Boolean true. The mechanism enables the consumer to trace signal submissions of the producers such that submission traversals by the producers and trace traversals by the consumer can be concurrently performed to allow data races between signal submissions by producers and between signal submissions by producers and the consumer.

Abstract: A method for hierarchical very large scale integration design comprises representing a structure of the hierarchical very large scale integrated design as a graph comprising design objects. The method further comprises specifying a transformation behavior applied to the design objects, and processing, top-down, the graph to perform the transformation on the hierarchical very large scale integrated design.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A method for hierarchical very large scale integration design comprises representing a structure of the hierarchical very large scale integrated design as a graph comprising design objects. The method further comprises specifying a transformation behavior applied to the design objects, and processing, top-down, the graph to perform the transformation on the hierarchical very large scale integrated design.

Abstract: A method and system for generating memory array bitmaps is disclosed that uses the memory binary address and failing memory data bits collected during test of a chip as input and translates this input directly to physical location in physical design formats which uses memory and a logical to physical server in an electronic computer aided design system.

Abstract: A method and system for generating memory array bitmaps is disclosed that uses the memory binary address and failing memory data bits collected during test of a chip as input and translates this input directly to physical location in the GDSII and/or GL1 physical design formats which uses memory and a logical to physical server in an electronic computer aided design system.

Abstract: A single pattern-matching algorithm which allows both exact and inexact pattern-matching so that transistor-level design automation tools can reliably perform timing analysis, electrical rules checking, noise analysis, test pattern generation, formal design verification, and the like prior to manufacturing custom logic. The user (circuit designer) specifies which of each of the pattern external nets may be matched inexactly (attached to Vdd, attached to GND, and shorted to other external nets), with the remainder of the pattern external net connections being matched using exact isomorphism constraints. The method described herein achieves a substantial reduction in the number of patterns which circuit designers must generate, and altogether eliminates the need for an exponential number of patterns by providing an inexact pattern matcher to circuit designers.