Abstract: Techniques that facilitate model support in deep learning are provided. In one example, a system includes a graphics processing unit and a central processing unit memory. The graphics processing unit processes data to train a deep neural network. The central processing unit memory stores a portion of the data to train the deep neural network. The graphics processing unit provides, during a forward pass process of the deep neural network that traverses through a set of layers for the deep neural network from a first layer of the set of layers to a last layer of the set of layers that provides a set of outputs for the deep neural network, input data for a layer from the set of layers for the deep neural network to the central processing unit memory.

Abstract: Techniques that facilitate model support in deep learning are provided. In one example, a system includes a graphics processing unit and a central processing unit memory. The graphics processing unit processes data to train a deep neural network. The central processing unit memory stores a portion of the data to train the deep neural network. The graphics processing unit provides, during a forward pass process of the deep neural network that traverses through a set of layers for the deep neural network from a first layer of the set of layers to a last layer of the set of layers that provides a set of outputs for the deep neural network, input data for a layer from the set of layers for the deep neural network to the central processing unit memory.

Abstract: Techniques for image processing and transformation are provided. A plurality of images and a plurality of maps are received, and a system of neural networks is trained based on the plurality of images and the plurality of maps. A first image is received, and a first map is generated by processing the first image using the system of neural networks.

Abstract: Techniques that facilitate model support in deep learning are provided. In one example, a system includes a graphics processing unit and a central processing unit memory. The graphics processing unit processes data to train a deep neural network. The central processing unit memory stores a portion of the data to train the deep neural network. The graphics processing unit provides, during a forward pass process of the deep neural network that traverses through a set of layers for the deep neural network from a first layer of the set of layers to a last layer of the set of layers that provides a set of outputs for the deep neural network, input data for a layer from the set of layers for the deep neural network to the central processing unit memory.

Abstract: An embodiment includes identifying an initial plurality of sets of hyperparameter values at which to evaluate an objective function that relates hyperparameter values to performance values of a neural network. The embodiment also executes training processes on the neural network with the hyperparameters set to the each of the initial sets of hyperparameter values such that the training process provides an initial set of the performance values for the objective function. The embodiment also generates an approximation of the objective function using splines at selected performance values. The embodiment approximates a point at which the approximation of the objective function reaches a maximum value, then determines an updated set of hyperparameter values associated with the maximum value. The embodiment then executes a runtime process using the neural network with the hyperparameters set to the updated set of hyperparameter values.

Abstract: Techniques for image processing and transformation are provided. A plurality of images and a plurality of maps are received, and a system of neural networks is trained based on the plurality of images and the plurality of maps. A first image is received, and a first map is generated by processing the first image using the system of neural networks.

Abstract: A parallel execution method, system, and non-transitory computer readable medium, include creating a continuum where the continuum includes a construct that holds data structures and where the continuum enables redirection of memory allocation and deallocation within a marked code section of a virtual address range.

Abstract: An iterative graph algorithm accelerating method, system, and computer program product, include recording an order of access nodes in a memory layout, reordering the access nodes in the memory layout in accordance with the recorded order, and updating edge information of the reordered access nodes.

Abstract: Techniques that facilitate model support in deep learning are provided. In one example, a system includes a graphics processing unit and a central processing unit memory. The graphics processing unit processes data to train a deep neural network. The central processing unit memory stores a portion of the data to train the deep neural network. The graphics processing unit provides, during a forward pass process of the deep neural network that traverses through a set of layers for the deep neural network from a first layer of the set of layers to a last layer of the set of layers that provides a set of outputs for the deep neural network, input data for a layer from the set of layers for the deep neural network to the central processing unit memory.

Abstract: A parallel execution method, system, and non-transitory computer readable medium not maintaining a cache coherence, include creating a continuum, the continuum being a construct that holds data structures, giving a view to the continuum, the view being a descriptor that provides access rights and properties for the continuum, and performing a task associated with an execution sequence, the task holding the view to the continuum that the execution sequence is accessing.

Abstract: A parallel execution method, system, and non-transitory computer readable medium, include creating a continuum where the continuum includes a construct that holds data structures and where the continuum enables redirection of memory allocation and deallocation within a marked code section of a virtual address range.

Abstract: An iterative graph algorithm accelerating method, system, and computer program product, include recording an order of access nodes in a memory layout, reordering the access nodes in the memory layout in accordance with the recorded order, and updating edge information of the reordered access nodes.

Abstract: An iterative graph algorithm accelerating method, system, and computer program product, include recording an order of access nodes in a memory layout, reordering the access nodes in the memory layout in accordance with the recorded order, and updating edge information of the reordered access nodes.

Abstract: An iterative graph algorithm accelerating method, system, and computer program product, include recording an order of access nodes in a memory layout, reordering the access nodes in the memory layout in accordance with the recorded order, and updating edge information of the reordered access nodes.

Abstract: A parallel execution method, system, and non-transitory computer readable medium not maintaining a cache coherence, include creating a continuum, the continuum being a construct that holds data structures, giving a view to the continuum, the view being a descriptor that provides access rights and properties for the continuum, and performing a task associated with an execution sequence, the task holding the view to the continuum that the execution sequence is accessing.

Abstract: A system and method for correlation of resources with hardware events includes event driven sampling a call chain of functions to determine when functions of the call chain are active. The call chain is mapped to execution times based upon a probabilistic integration of the functions such that when portions of the call chain are active, resources associated with call chain activity are correlated with hardware events.

Abstract: Techniques for storage allocation of a data record are provided. The techniques include attempting to identify a first location for storing a data record, wherein the data record comprises one or more data record attributes, if the first location is identified, selecting the first location for storing the data record, and if the first location is not identified, identifying a second location for storing the data record using a cost penalty function and selecting the second location for storing the data record based on the cost penalty function.

Abstract: Techniques for storage allocation of a data record are provided. The techniques include attempting to identify a first location for storing a data record, wherein the data record comprises one or more data record attributes, if the first location is identified, selecting the first location for storing the data record, and if the first location is not identified, identifying a second location for storing the data record using a cost penalty function and selecting the second location for storing the data record based on the cost penalty function.

Abstract: A system and method for correlation of resources with hardware events includes event driven sampling a call chain of functions at to determine when functions of the call chain are active. The call chain is mapped to execution times based upon a probabilistic integration of the functions such that when portions of the call chain are active, resources associated with call chain activity are correlated with hardware events.

Abstract: Tracing a short as a shortest path of explicit VLSI design component instances between two VLSI design component instances with different net names in a hierarchical design is a non-hierarchical problem. The method described in this document computes a shortest path of VLSI design leaf component instances containing at least one of the leaf design components causing the sort. To avoid exceeding available storage, the non-hierarchical instance information maintained during the process is pruned optimally. To achieve feasible performance, two methods to find “good” starting points are provided, based on geometrical distribution or based on connectivity information from the net build (if available).