Abstract: Operating IO-Link system having wirelessly connected IO-Link masters and several IO-Link devices divided into groups wirelessly connected by control system, at least one master with different configurations, one master with first configuration to operate first group of devices; a first process loop connected between at least one master and first group devices, checking communication status of connected devices of first group; at least second process loop reading devices of first group, setting configuration values for operation of first group devices, at least one master with at least second configuration operates at least second group of devices; at least third process loop connected between at least one master and devices of at least second group devices, checking communication status of connected devices of at least second group devices; at least fourth process loop reading devices of at least second group, setting configuration values for operation of at least second group devices.

Abstract: An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.

Abstract: An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.

Abstract: LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, MCM, and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the overall power consumption because weighted LBIST testing consumes much less power than flat LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.

Abstract: The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages (10) of a semiconductor chip. Two dedicated support transistor devices (56, 58) are added into the prior art switching scheme, together with a simple control logic (48, 50, 52, 60, 62, 64) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver (24) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.

Abstract: For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated.

Abstract: The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip. Electrical properties, as for example DC-resistance, AC-impedance of a driver stage are tested by at least one test load implemented on the chip itself which causes a characteristic voltage drop usable for test evaluation. Advantageously, the output stage devices of P-type (50, 52) and N-type (54, 56), respectively, are split into at least two sub-devices P1, P2 and N1, N2, and are controlled separately by a control logic (60, 62, 64, 70, 72, 74). Then, for example N2 is used for testing the P device, and P2 is used for testing the N-device. Thus, devices already present on the chip are re-used for test purposes, which makes off-chip testing unnecessary.

Abstract: The present invention, enables complementing the state of either the master (L1) or slave latch (L2) in the shift register latches (SRLs) without changing the state of the other. When this is done after properly loading the LSSD scan chain using a normal scan chain sequence, the next system clock sequence can be used to launch a desired transition from each SRL in the scan chain. The actual mechanism for complementing the state of latches in LSSD scan chains can vary depending on which one of the L1 or L2 latch is being complemented; details of the actual scan chain and Shift Register Latch (SRL) design; and the semiconductor chip circuit technology. The complementing function can be provided as an integral part of the SRL design with minimal impact to system path and performance. An alternate complementing method would be to use a self complementing latch function.

Abstract: LBIST and weighted LBIST tests are performed simultaneously on different portions of the tested object. This new test methodology and design change achieves the same test coverage and test time as the traditional test strategy with dramatic power reduction during test. It can be applied at wafer, chip, MCM, and system levels of test. Most importantly, it does not need new tools for support. Current test software will work as it does with the traditional test strategy. Scheduling the LBIST and weighted LBIST tests in the same test session reduces the overall power consumption because weighted LBIST testing consumes much less power than flat LBIST testing. In the same test session, if some parts of the logic is tested using weighted LBIST while the others were tested using LBIST, the power consumed by the circuit element at any given time is reduced.

Abstract: The present invention relates to a test for current leakage of driver/receiver stages, and in particular for bi-directional input/output stages (10) of a semiconductor chip. Two dedicated support transistor devices (56, 58) are added into the prior art switching scheme, together with a simple control logic (48, 50, 52, 60, 62, 64) for selectively controlling the two dedicated support transistor devices according to a predetermined test scheme. An on-chip self-test feature provides valid voltage levels which are convertible by the receiver (24) to predictable logic states at the evaluation line RDATA. The test can be performed autonomously on the chip without the requirement for an external test device.

Abstract: For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated.

Abstract: The present invention relates to a method and system for full parametric testing of the drive and receive capability of bi-directional driver/receiver-stages, and in particular of bi-directional input/output-stages of a semiconductor chip. Electrical properties, as for example DC-resistance, AC-impedance of a driver stage are tested by at least one test load implemented on the chip itself which causes a characteristic voltage drop usable for test evaluation. Advantageously, the output stage devices of P-type(50, 52) and N-type(54,56), respectively, are split into at least two sub-devices P1, P2 and N1, N2, and are controlled separately by a control logic (60,62,64,70,72,74). Then, for example N2 is used for testing the P device, and P2 is used for testing the N-device. Thus, devices already present on the chip are re-used for test purposes, which makes off-chip testing unnecessary.

Abstract: A pressure sensor has a movable diaphragm stretched directly between the annular pressing surfaces of two housing parts, and an electrical measuring device. In an area that is located radially outward as viewed from the pressing surfaces, the diaphragm has a sealing ring that abuts both housing parts. As a result, transverse vibrations of the diaphragm are reliably supported.