Abstract: A system includes a processor with a front end to receive an instruction stream reordered by a software scheduler and including a plurality of memory operations and alias information indicating how a given memory operation may be evaluated. Furthermore, the processor includes a hardware scheduler to reorder, in hardware, the instruction stream for out-of-order execution. In addition, the processor includes a calculation module to determine, for a given memory operation and based upon the alias information, a checking range of memory atoms subsequent to the given memory operation and a virtual order of the memory operation. The virtual order indicates an original ordering of the instructions. The processor also includes an alias unit to reorder the instruction stream, determine whether the hardware reordering caused an error, and determine whether the software reordering caused an error based upon the checking range and the virtual order.

Abstract: A system includes a processor with a front end to receive an instruction stream reordered by a software scheduler and including a plurality of memory operations and alias information indicating how a given memory operation may be evaluated. Furthermore, the processor includes a hardware scheduler to reorder, in hardware, the instruction stream for out-of-order execution. In addition, the processor includes a calculation module to determine, for a given memory operation and based upon the alias information, a checking range of memory atoms subsequent to the given memory operation and a virtual order of the memory operation. The virtual order indicates an original ordering of the instructions. The processor also includes an alias unit to reorder the instruction stream, determine whether the hardware reordering caused an error, and determine whether the software reordering caused an error based upon the checking range and the virtual order.

Abstract: Embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic frequency modulation. In one embodiment, an apparatus comprises a first cell comprising a chaotic signal generator to generate a chaotic signal and a phase-locked loop (PLL) to generate a modulated output signal based at least on an un-modulated reference signal and the chaotic signal.

Abstract: The embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic wide band frequency modulation. The chaotic noise modulator, in one embodiment, comprises: a master cell to generate a control voltage corresponding to an un-modulated reference signal; and a slave cell having a chaotic signal generator to generate a random noise signal, the slave cell coupled with the master cell and operable to generate a modulated output signal in response to the control voltage.

Abstract: Embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic frequency modulation. In one embodiment, an apparatus comprises a first cell comprising a chaotic signal generator to generate a chaotic signal and a phase-locked loop (PLL) to generate a modulated output signal based at least on an un-modulated reference signal and the chaotic signal.

Abstract: The embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic wide band frequency modulation. The chaotic noise modulator, in one embodiment, comprises: a master cell to generate a control voltage corresponding to an un-modulated reference signal; and a slave cell having a chaotic signal generator to generate a random noise signal, the slave cell coupled with the master cell and operable to generate a modulated output signal in response to the control voltage.