Abstract: In one embodiment, a system receives an exec function invocation request from a second application to run a first application from an executable file. In response to receiving the exec function invocation request, the system determines a working directory associated with the second application. The system determines one or more extended attribute values associated with the working directory. The system determines, in view of the one or more extended attribute values, whether to allow or deny the first application to use the working directory to run the executable file of the first application.

Abstract: Systems and methods for supporting a compilation framework for hardware configuration generation. In one implementation, a processing device executing a compilation workflow for a target architecture may receive an input source code associated with a configuration for the target hardware architecture; identify a first configuration information associated with at least a portion of the configuration for the target hardware architecture; perform a first set of compilation passes of the input source code in view of the first configuration information; generate, in view of the first set of compilation passes of the input source code, a first internal representation component for the target hardware architecture; and generate, in view of the first internal representation component, a binary bitstream component for the target hardware architecture.

Abstract: Systems and methods for configuration management through information and code injection at compile time. An example method comprises: receiving a source code comprising one or more references to a variable; receiving metadata associated with the source code, wherein the metadata specifies a range of values of the variable; and identifying, in view of the range of values of the variable, a reachable section of the source code.

Abstract: Systems and methods for configuration management through information and code injection at compile time. An example method comprises: receiving a source code comprising one or more references to a variable; receiving metadata associated with the source code, wherein the metadata specifies a range of values of the variable; and identifying, in view of the range of values of the variable, a reachable section of the source code.

Abstract: A method of launching a unikernel comprises: identifying, by a kernel utilizing a set of system resources of a computing system, a unikernel to be launched in an exclusive mode; determining that the set of system resources of the computing system satisfies hardware requirements specified by configuration metadata of the unikernel; releasing, by the kernel, the set of system resources for use by the unikernel; launching the unikernel; and terminating the kernel.

Abstract: Systems and methods for configuration management through information and code injection at compile time. An example method comprises: receiving a source code comprising one or more references to a variable; receiving metadata associated with the source code, wherein the metadata specifies a range of values of the variable; and identifying, in view of the range of values of the variable, a reachable section of the source code.

Abstract: An instruction offload manager receives, by a processing device, a first request to execute a program, identifies one or more instructions of the program to be offloaded to a second processing device, where the second processing device includes a same instruction set architecture as the processing device, and provides the one or more instructions to a memory module comprising the second processing device. Responsive to detecting an indication to execute the one or more instructions, the instruction offload manager provides an indication to the second processing device to cause the second processing device to execute the one or more instructions, the one or more instructions to update a portion of a memory space associated with the memory module.

Abstract: An apparatus includes multiple parallel computing cores, where each computing core is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple sets of parallel coprocessors, where each computing core is associated with a different one of the sets of parallel coprocessors. The coprocessors in each set of parallel coprocessors are configured to process the input data and generate output data. Each of the computing cores is configured to generate additional input data based on the output data generated by the associated set of parallel coprocessors.

Abstract: In one embodiment, a method may receive, by a compiler of a host computing system, source code for a computer application. The method may also include separating a first portion of the source code and a second portion of the source code that are to be compiled for execution by an accelerator operatively coupled to the host computing system. The method may also include compiling the first portion of the source code to generate hardware description language code. A logic block is to be generated on the accelerator in view of the hardware description language code. The method also includes compiling the second portion of the source code to generate softcore processor code, and adding instructions to the softcore processor code to cause the softcore processor code to interact with the logic block during execution of the softcore processor code and the logic block.

Abstract: A method of launching a unikernel comprises: identifying, by a kernel utilizing a set of system resources of a computing system, a unikernel to be launched in an exclusive mode; determining that the set of system resources of the computing system satisfies hardware requirements specified by configuration metadata of the unikernel; releasing, by the kernel, the set of system resources for use by the unikernel; launching the unikernel; and terminating the kernel.

Abstract: In one embodiment, a method may receive, by a compiler of a host computing system, source code for a computer application. The method may also include separating a first portion of the source code and a second portion of the source code that are to be compiled for execution by an accelerator operatively coupled to the host computing system. The method may also include compiling the first portion of the source code to generate hardware description language code. A logic block is to be generated on the accelerator in view of the hardware description language code. The method also includes compiling the second portion of the source code to generate softcore processor code, and adding instructions to the softcore processor code to cause the softcore processor code to interact with the logic block during execution of the softcore processor code and the logic block.

Abstract: An apparatus includes multiple parallel computing cores, where each computing core is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple parallel coprocessors associated with each computing core. The apparatus further includes multiple communication lines configured to transport the input data from each computing core to a designated one of the coprocessors associated with each of the computing cores, where the coprocessors are configured to process the input data and generate output data. In addition, the apparatus includes multiple reducer circuits, where each computing core is associated with one of the reducer circuits. Each reducer circuit is configured to receive the output data from each of the coprocessors of the associated computing core, to apply one or more functions to the output data, and to provide one or more results to the associated computing core.

Abstract: An apparatus includes multiple parallel computing cores, where each computing core is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple sets of parallel coprocessors, where each computing core is associated with a different one of the sets of parallel coprocessors. The coprocessors in each set of parallel coprocessors are configured to process the input data and generate output data. Each of the computing cores is configured to generate additional input data based on the output data generated by the associated set of parallel coprocessors.

Abstract: An apparatus includes multiple parallel computing cores, where each computing core is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple parallel coprocessors associated with each computing core. The apparatus further includes multiple communication lines configured to transport the input data from each computing core to a designated one of the coprocessors associated with each of the computing cores, where the coprocessors are configured to process the input data and generate output data. In addition, the apparatus includes multiple reducer circuits, where each computing core is associated with one of the reducer circuits. Each reducer circuit is configured to receive the output data from each of the coprocessors of the associated computing core, to apply one or more functions to the output data, and to provide one or more results to the associated computing core.

Abstract: An apparatus includes multiple computing cores, where each computing core is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple coprocessors associated with each computing core, where each coprocessor is configured to receive the input data from at least one of the computing cores, process the input data, and generate output data. The apparatus further includes multiple reducer circuits, where each reducer circuit is configured to receive the output data from each of the coprocessors of an associated computing core, apply one or more functions to the output data, and provide one or more results to the associated computing core. In addition, the apparatus includes multiple communication links communicatively coupling the computing cores and the coprocessors associated with the computing cores.

Abstract: An apparatus includes multiple parallel computing cores, where each computing core is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple parallel coprocessors associated with each computing core. The apparatus further includes multiple communication lines configured to transport the input data from each computing core to a designated one of the coprocessors associated with each of the computing cores, where the coprocessors are configured to process the input data and generate output data. In addition, the apparatus includes multiple reducer circuits, where each computing core is associated with one of the reducer circuits. Each reducer circuit is configured to receive the output data from each of the coprocessors of the associated computing core, to apply one or more functions to the output data, and to provide one or more results to the associated computing core.

Abstract: An apparatus includes multiple parallel computing cores, where each computing core is configured to perform one or more processing operations and generate input data. The apparatus also includes multiple parallel coprocessors associated with each computing core. The apparatus further includes multiple communication lines configured to transport the input data from each computing core to a designated one of the coprocessors associated with each of the computing cores, where the coprocessors are configured to process the input data and generate output data. In addition, the apparatus includes multiple reducer circuits, where each computing core is associated with one of the reducer circuits. Each reducer circuit is configured to receive the output data from each of the coprocessors of the associated computing core, to apply one or more functions to the output data, and to provide one or more results to the associated computing core.

Abstract: A system receives a notification that a process is requesting access to a file stored in a file system, wherein the process is currently delayed from accessing the file. The system determines whether a current file attribute setting for the requested file is correct in response to receiving the notification and changes the current file attribute setting to a correct file attribute setting in response to determining that the current file attribute setting is not correct. The system sends a notification to allow the process to resume to access the file in response determining that the current file attribute setting is correct or changing the current file attribute setting to the correct file attribute setting.

Abstract: Methods and systems for managing program-level parallelism in a multi-core processor environment are provided. The methods for managing parallel execution of processes associated with computer programs include providing an agent process in an application space, which is operatively coupled to an operating system having a kernel configured to determine processor configuration information. The application space may be a runtime environment or a user space of the operating system, and has a lower privilege level than the kernel. The agent process retrieves the processor configuration information from the kernel, and after receiving a request for the processor configuration information from application processes running in the application space, the agent process provides a response to the requesting application process.

Abstract: An embodiment generally pertains to a method of secure address handling in a processor. The method includes detecting an instruction that implicitly designates a target address and retrieving an encoded location associated with the target address. The method also includes decoding the encoded location to determine the target address. Another embodiment generally relates to detecting an instruction having an operand designating an encoded target address and determining a location of a target instruction associated with the target address. The method also includes determining a location of a subsequent instruction and encoding the location of the subsequent instruction. The method further includes storing the encoded location of the subsequent instruction.