Abstract: A method of synthesizing semiconductor nanostructures of at least one semiconductor material (e.g. nanowires, nanorods, nanoribbons, nanodots, quantumdots, etc.) is described which includes the steps of placing a solid catalyst particle on a substrate, placing the combination of the said substrate and the said solid catalyst in a chamber of low oxygen partial pressure, below I×10?2 mbar, adding one or more gaseous reactants comprising at least one of said semiconductor material and a suitable precursor therefor and heating the said combination to a temperature above 200° C. but below the melting point of the solid catalyst particle. Nanostructures made by the method are also claimed.

Abstract: A structure containing a ferroelectric material comprises a substrate such as silicon, a buffer layer formed on the substrate, and a non-c-axis-oriented, electrically-conductive template layer formed on the buffer layer. The template layer comprises a perovskite oxide compound. An epitaxially a-axis-oriented ferroelectric layer is formed on the template layer, and has a vector of spontaneous polarization oriented perpendicular or at least substantially perpendicular to the film normal.

Abstract: A method is described for the production of a suitable substrate for the subsequent growth of a mono-crystalline diamond layer. This method includes the following steps: Selection of a substrate of a mono-crystalline material having a fixed lattice constant (aSi) or with a layer consisting of such a material. Manufacture of a strained silicon layer with foreign material atoms incorporated at substitutional lattice sites on the mono-crystalline material of the substrate. Transfer of the strained layer into an at least partly relaxed state in which it adopts by relaxation and through the selected foreign material concentration a lattice constant (aSi(C) which satisfies the condition n.aSi(C)=m.aD, wherein n and m are integers and aD is the lattice constant of diamond, with the relaxed layer forming the substrate or substrate surface for the epitaxial growth.

Abstract: A structure containing a ferroelectric material comprises a substrate comprising silicon, a buffer layer formed on the substrate, and a non-c-axis-oriented, electrically-conductive template layer formed on the buffer layer. The template layer comprises a perovskite oxide compound. A non-c-axis-oriented, anisotropic perovskite ferroelectric layer is formed on the template layer.

Abstract: Cleaning in periodic acid (H.sub.5 IO.sub.6) aqueous solutions (HI solutions) of particular compositions removes thermally unstable hydrocarbons from the surfaces of semiconductor wafers and enables the direct bonding of semiconductor surfaces such that the bonded interface between these surfaces remains free of bubbles even after heating subsequent to bonding.

Abstract: A semiconductor region that is inserted into a semiconductor member is provided, the latter being separated from the former by a planar pn junction including a first, more highly doped sub-region and a second, more lightly doped sub-region that is limited by a part of the pn junction that gradually approaches a boundary surface of the semiconductor member. An electrode contacts the semiconductor region and covers a part of the second sub-region and extends toward the lateral limitation of the semiconductor region to such an extent that, given the application of a voltage inhibiting the pn junction the space charge zone forming thereat has its edge lying in the boundary surface just reaching the electrode edge given a reduced breakdown voltage.

Abstract: A method for the manufacture of a pn junction having a high breakdown voltage at the boundary surface of a semiconductor body, utilizing a mask which has a relatively large opening for introducing a dopant therethrough into the semiconductor body, the mask having a marginal edge which extends laterally beyond the edge of the relatively large opening. In the marginal edge, the mask is provided with smaller, auxiliary openings, the openings being sized and spaced such that lesser amounts of dopant pass through the opening as the distance of the auxiliary openings from the edge of the relatively larger opening increases. Upon introducing the dopant into the semiconductor body through the mask, there is generated a doping profile which gradually approaches the boundary surface with increasing distance from the edge of the relatively large opening.