Abstract: A carrier compensation reader compensates a carrier signal. The carrier compensation reader transmits, via an antenna, a first carrier signal and obtains a second carrier signal based on the first carrier signal. The carrier compensation reader configures a compensation circuit to receive a receiver output signal based on the second carrier signal and generate a compensation signal based on the receiver output signal to compensate the second carrier signal. The carrier compensation reader obtains a carrier compensation signal summing the second carrier signal and the compensation signal.

Abstract: A receiving circuit, use, and method for receiving an encoded and modulated radio signal is provided. The circuit comprise a demodulator and a digital filter connected downstream of the demodulator for moving averaging. The filter has at least two FIFO registers and subtractors. Whereby for subtracting an output value of the FIFO register from an input value of the FIFO register a subtractor is connected to each FIFO register. Wherein the filter has a weighting unit, which is connected downstream of each FIFO register, and wherein the filter has an integrator, which is connected downstream of the subtractors for integration.

Abstract: A circuit, use, and method for controlling a receiver circuit is provided, wherein a complex baseband signal is generated from a received signal, a phase difference between a phase of the complex baseband signal and a phase precalculated from previous sampled values is determined, the phase difference is compared with a first threshold, a number is determined by counting the exceedances of the first threshold by the phase difference, a number of the counted exceedances is compared with a second threshold, and the receiver circuit is turned off if the number of counted exceedances exceeds the second threshold within a time period.

Abstract: A carrier compensation reader compensates a carrier signal. The carrier compensation reader transmits, via an antenna, a first carrier signal and obtains a second carrier signal based on the first carrier signal. The carrier compensation reader configures a compensation circuit to receive a receiver output signal based on the second carrier signal and generate a compensation signal based on the receiver output signal to compensate the second carrier signal. The carrier compensation reader obtains a carrier compensation signal summing the second carrier signal and the compensation signal.

Abstract: A method for controlling a receiver circuit and circuit with a receiver circuit and with a control circuit is provided, whereby a received signal is demodulated and filtered. An amplitude value of the demodulated and filtered signal is compared with thresholds of a window comparator. A zero crossing of the demodulated and filtered signal is compared with time thresholds of a time window by a comparison unit. A first output value of the window comparator and a second output value of the comparison unit are logically combined, and wherein, via the logical combination, the receiver circuit is turned off if, within a period of time, the amplitude value is determined to be outside a window formed by the thresholds of the window comparator, or a zero crossing is determined to be outside the time window.

Abstract: A circuit, use, and method for controlling a receiver circuit is provided, wherein a complex baseband signal is generated from a received signal, a phase difference between a phase of the complex baseband signal and a phase precalculated from previous sampled values is determined, the phase difference is compared with a first threshold, a number is determined by counting the exceedances of the first threshold by the phase difference, a number of the counted exceedances is compared with a second threshold, and the receiver circuit is turned off if the number of counted exceedances exceeds the second threshold within a time period.

Abstract: A receiving circuit, use, and method for receiving an encoded and modulated radio signal is provided. The circuit comprise a demodulator and a digital filter connected downstream of the demodulator for moving averaging. The filter has at least two FIFO registers and subtractors. Whereby for subtracting an output value of the FIFO register from an input value of the FIFO register a subtractor is connected to each FIFO register. Wherein the filter has a weighting unit, which is connected downstream of each FIFO register, and wherein the filter has an integrator, which is connected downstream of the subtractors for integration.

Abstract: A circuit, use, and method for controlling a receiver circuit is provided, wherein a complex baseband signal is generated from a received signal, a phase difference between a phase of the complex baseband signal and a phase precalculated from previous sampled values is determined, the phase difference is compared with a first threshold, a number is determined by counting the exceedances of the first threshold by the phase difference, a number of the counted exceedances is compared with a second threshold, and the receiver circuit is turned off if the number of counted exceedances exceeds the second threshold within a time period.

Abstract: A receiving circuit, use, and method for receiving an encoded and modulated radio signal is provided. The circuit comprise a demodulator and a digital filter connected downstream of the demodulator for moving averaging. The filter has at least two FIFO registers and subtractors. Whereby for subtracting an output value of the FIFO register from an input value of the FIFO register a subtractor is connected to each FIFO register. Wherein the filter has a weighting unit, which is connected downstream of each FIFO register, and wherein the filter has an integrator, which is connected downstream of the subtractors for integration.

Abstract: A receiver circuit, application of a first proportional element and a second proportional element of a digital PLL structure, and method for receiving a frequency-shift keyed signal are provided. A phase signal is calculated from an in-phase signal and a quadrature signal. A feedback signal is subtracted from the phase signal to form a difference signal. An output signal is determined from the difference signal by a nonlinear transfer function. The output signal is evaluated with an evaluation circuit. A first signal and a second signal are added to form a summation signal. The first signal is produced by multiplication of the output signal or the difference signal by a first proportionality factor. The second signal is produced by multiplication of the output signal or the first signal or the difference signal by a second proportionality factor, followed by integration, and the feedback signal is produced by integration of the summation signal.

Abstract: A signal processing device and signal processing method is provided that includes a detection unit for detecting a signal strength of a signal, whereby the detection unit is configured to output a detection value that represents the signal strength of the signal; a settable digital filter connected upstream of the detection unit, whereby filter coefficients for setting a transfer characteristic of the filter are assigned to an amplification or attenuation of the signal by the filter; a digital multiplication unit, which is connected upstream of the detection unit for amplification or attenuation of the signal, whereby the multiplication unit is configured to compensate partially for the amplification or attenuation of the filter, whereby the compensation is encumbered with a residual error; and a correction unit to apply to the detection value a correction value at least partially compensating for the residual error.

Abstract: A receiving circuit and method for receiving an amplitude shift keying signal is provided. At least one exponent signal, an exponent-removed in-phase signal, and an exponent-removed quadrature-phase signal are generated from an in-phase input signal and a quadrature-phase input signal. An amplitude is determined as a sum of several summands, whereby the summands are determined from the exponent signal and/or from the exponent-removed in-phase signal and/or from the exponent-removed quadrature-phase signal (Q?), and wherein the amplitude (A) is demodulated.

Abstract: A method for controlling a receiver circuit and circuit with a receiver circuit and with a control circuit is provided, whereby a received signal is demodulated and filtered. An amplitude value of the demodulated and filtered signal is compared with thresholds of a window comparator. A zero crossing of the demodulated and filtered signal is compared with time thresholds of a time window by a comparison unit. A first output value of the window comparator and a second output value of the comparison unit are logically combined, and wherein, via the logical combination, the receiver circuit is turned off if, within a period of time, the amplitude value is determined to be outside a window formed by the thresholds of the window comparator, or a zero crossing is determined to be outside the time window.

Abstract: A circuit, use, and method for controlling a receiver circuit is provided, wherein a complex baseband signal is generated from a received signal, a phase difference between a phase of the complex baseband signal and a phase precalculated from previous sampled values is determined, the phase difference is compared with a first threshold, a number is determined by counting the exceedances of the first threshold by the phase difference, a number of the counted exceedances is compared with a second threshold, and the receiver circuit is turned off if the number of counted exceedances exceeds the second threshold within a time period.

Abstract: A receiving circuit, use, and method for receiving an encoded and modulated radio signal is provided. The circuit comprise a demodulator and a digital filter connected downstream of the demodulator for moving averaging. The filter has at least two FIFO registers and subtractors. Whereby for subtracting an output value of the FIFO register from an input value of the FIFO register a subtractor is connected to each FIFO register. Wherein the filter has a weighting unit, which is connected downstream of each FIFO register, and wherein the filter has an integrator, which is connected downstream of the subtractors for integration.

Abstract: A transducer device for converting an analog DC voltage signal into a digital signal is provided, with an oscillator device for outputting a first oscillator signal and a second oscillator signal, whereby the oscillator device is formed to generate the first oscillator signal and the second oscillator signal phase-locked to one another and with the substantially same frequency from a reference signal, with an analog frequency converter connected to the oscillator device for transforming the analog DC voltage signal by the first oscillator signal in a first spectral range with a first center frequency to obtain a transformed signal, with an analog-to-digital converter for converting the transformed signal into a transformed digital signal; and with a digital frequency converter connected to the oscillator device for transforming the transformed digital signal by means of the second oscillator signal in a second spectral range with a second center frequency to obtain the digital signal.

Abstract: A receiving circuit and method for receiving an amplitude shift keying signal is provided. At least one exponent signal, an exponent-removed in-phase signal, and an exponent-removed quadrature-phase signal are generated from an in-phase input signal and a quadrature-phase input signal. An amplitude is determined as a sum of several summands, whereby the summands are determined from the exponent signal and/or from the exponent-removed in-phase signal and/or from the exponent-removed quadrature-phase signal (Q?), and wherein the amplitude (A) is demodulated.

Abstract: A receiver circuit, application of a first proportional element and a second proportional element of a digital PLL structure, and method for receiving a frequency-shift keyed signal are provided. A phase signal is calculated from an in-phase signal and a quadrature signal. A feedback signal is subtracted from the phase signal to form a difference signal. An output signal is determined from the difference signal by a nonlinear transfer function. The output signal is evaluated with an evaluation circuit. A first signal and a second signal are added to form a summation signal. The first signal is produced by multiplication of the output signal or the difference signal by a first proportionality factor. The second signal is produced by multiplication of the output signal or the first signal or the difference signal by a second proportionality factor, followed by integration, and the feedback signal is produced by integration of the summation signal.

Abstract: A signal processing device and signal processing method is provided that includes a detection unit for detecting a signal strength of a signal, whereby the detection unit is configured to output a detection value that represents the signal strength of the signal; a settable digital filter connected upstream of the detection unit, whereby filter coefficients for setting a transfer characteristic of the filter are assigned to an amplification or attenuation of the signal by the filter; a digital multiplication unit, which is connected upstream of the detection unit for amplification or attenuation of the signal, whereby the multiplication unit is configured to compensate partially for the amplification or attenuation of the filter, whereby the compensation is encumbered with a residual error; and a correction unit to apply to the detection value a correction value at least partially compensating for the residual error.

Abstract: A transducer device for converting an analog DC voltage signal into a digital signal is provided, with an oscillator device for outputting a first oscillator signal and a second oscillator signal, whereby the oscillator device is formed to generate the first oscillator signal and the second oscillator signal phase-locked to one another and with the substantially same frequency from a reference signal, with an analog frequency converter connected to the oscillator device for transforming the analog DC voltage signal by the first oscillator signal in a first spectral range with a first center frequency to obtain a transformed signal, with an analog-to-digital converter for converting the transformed signal into a transformed digital signal; and with a digital frequency converter connected to the oscillator device for transforming the transformed digital signal by means of the second oscillator signal in a second spectral range with a second center frequency to obtain the digital signal.