Abstract: Aspects of the disclosure provide a semiconductor device and method of manufacturing. Embodiments of the disclosure enable placing of protective structures without modifying spacing rules. The device includes a first device region defined above a substrate, the first device region being isolated from the substrate by a buried insulating layer. The first device region includes a first power rail, a first signal line traversing at least a first portion of the first device region, and a first plurality of edge cells positioned in the substrate adjacent the first device region. A first edge cell includes a substrate contact connecting the first power rail to the substrate and a first signal line antenna diode connecting the first signal line to the substrate.

Abstract: A semiconductor device is disclosed including, among other things, a first device region defined above a substrate, wherein the first device region is isolated from the substrate by a buried insulating layer, the first device region including a first power rail, a first signal line traversing at least a first portion of the first device region, and a first plurality of edge cells positioned in the substrate adjacent the first device region, wherein at least a first edge cell of the first plurality of edge cells includes a substrate contact connecting the first power rail to the substrate and a first signal line antenna diode connecting the first signal line to the substrate.

Abstract: Structures for a circuit including field-effect transistors and methods for fabricating and operating such circuits. A plurality of logic cells with a first well and a second well. The first well is directly connected with ground. A tap cell includes an inverter having an output connected with the second well. The inverter is configured to provide a bias voltage having a first state in which a positive voltage is supplied to the second well and a second state in which the second well is connected with ground.

Abstract: The present disclosure provides a placing and routing method for implementing back bias in fully depleted silicon-on-insulator. In accordance with some illustrative embodiments herein, the placing and routing method comprises placing a first plurality of a standard tap well cell along a first direction, the standard tap well cell being formed by: routing a p-BIAS wire VPW and an n-BIAS wire VNW in a first a first metallization layer, and routing a power rail and a ground rail in a second metallization layer, the VPW and the VNW extending across each of the power and ground rail, wherein the VPWs of the first plurality of standard tap well cells are continuously connected and the VNWs of the first plurality of standard tap well cells are continuously connected.

Abstract: The present disclosure provides an integrated circuit product including a plurality of standard cells, each standard cell of the plurality of standard cells being in abutment with at least one other standard cell of the plurality of standard cells, a continuous active region continuously extending across the plurality of standard cells, at least two active regions being separated by an intermediate diffusion break, wherein each standard cell comprises at least one PMOS device and at least one NMOS device, the at least one PMOS device being provided in and above the continuous active region and the at least one NMOS device being provided in and above the at least two active regions.

Abstract: It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.

Abstract: It is provided a semiconductor device comprising a power line, a Silicon-on-Insulator, SOI, substrate comprising a semiconductor layer and a semiconductor bulk substrate comprising a first doped region, a first transistor device formed in and above the SOI substrate and comprising a first gate dielectric formed over the semiconductor layer and a first gate electrode formed over the gate dielectric, a first diode electrically connected to the first gate electrode and a second diode electrically connected to the first diode and the power line; and wherein the first and second diodes are partially formed in the first doped region.

Abstract: The present disclosure provides a placing and routing method for implementing back bias in fully depleted silicon-on-insulator. In accordance with some illustrative embodiments herein, the placing and routing method comprises placing a first plurality of a standard tap well cell along a first direction, the standard tap well cell being formed by: routing a p-BIAS wire VPW and an n-BIAS wire VNW in a first a first metallization layer, and routing a power rail and a ground rail in a second metallization layer, the VPW and the VNW extending across each of the power and ground rail, wherein the VPWs of the first plurality of standard tap well cells are continuously connected and the VNWs of the first plurality of standard tap well cells are continuously connected.

Abstract: A method includes obtaining a plurality of design rules for an integrated circuit, including a first set of design rules and a second set of design rules. An automated layout construction process performed on the basis of the first set of design rules but not on the basis of the second set of design rules creates a layout of the integrated circuit. The layout of the integrated circuit is checked for design rule violations wherein at least one member of the second set of design rules is not satisfied. The layout of the integrated circuit is modified for bringing the layout into conformity with each of the plurality of design rules if one or more design rule violations are found in the checking of the integrated circuit.

Abstract: A method includes obtaining a plurality of design rules for an integrated circuit, including a first set of design rules and a second set of design rules. An automated layout construction process performed on the basis of the first set of design rules but not on the basis of the second set of design rules creates a layout of the integrated circuit. The layout of the integrated circuit is checked for design rule violations wherein at least one member of the second set of design rules is not satisfied. The layout of the integrated circuit is modified for bringing the layout into conformity with each of the plurality of design rules if one or more design rule violations are found in the checking of the integrated circuit.

Abstract: A WLAN (Wireless Local Area Network) communication device and method are provided where a MAC (Medium Access Control) control unit controls access to a wireless medium. The MAC control unit is capable of selectively applying any one of at least two different control mechanisms to data to be transmitted. The data received from a target system comprises data frames, each having associated an individual control header comprising control information. The control information specifies at least one control mechanism to be applied to data of the associated data frame. The MAC control unit extracts control information from each control header associated to a data frame, and selects a control mechanism specified by the extracted control information.