Abstract: A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.

Abstract: In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.

Abstract: In some aspects, a mask pattern is accessed. The mask pattern is for use in a lithography process that prints a pattern on a wafer. The mask pattern is applied as input to a deterministic model of the lithography process to predict a characteristic of the printed pattern. The deterministic model is deterministic, but it accounts for local stochastic variations of the characteristic in the printed pattern.

Abstract: Certain aspects relate to a method for improving a lithography configuration. In the lithography configuration, a source illuminates a mask to expose resist on a wafer. A processor determines a defect-based focus exposure window (FEW). The defect-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of defects on the wafer. The defect-based FEW is determined based on a predicted probability distribution for occurrence of defects on the wafer. A processor also determines a critical dimension (CD)-based FEW. The CD-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of CD variation on the wafer. It is determined based on predicted CDs on the wafer. The lithography configuration is modified based on increasing an area of overlap between the defect-based FEW and the CD-based FEW.

Abstract: A calibrated lithographic model may be used to generate a lithographic model output based on an integrated circuit (IC) design layout. Next, at least a chemical parameter may be extracted from the lithographic model output. A calibrated defect rate model may then be used to predict a defect rate for the IC design layout based on the chemical parameter.

Abstract: Certain aspects relate to a method for improving a lithography configuration. In the lithography configuration, a source illuminates a mask to expose resist on a wafer. A processor determines a defect-based focus exposure window (FEW). The defect-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of defects on the wafer. The defect-based FEW is determined based on a predicted probability distribution for occurrence of defects on the wafer. A processor also determines a critical dimension (CD)-based FEW. The CD-based FEW is an area of depth of focus and exposure latitude for the lithography configuration with an acceptable level of CD variation on the wafer. It is determined based on predicted CDs on the wafer. The lithography configuration is modified based on increasing an area of overlap between the defect-based FEW and the CD-based FEW.

Abstract: A method (and structure) of thermally treating a magnetic layer of a wafer, includes annealing, for a predetermined short duration, a magnetic layer of a single wafer.

Abstract: A method (and structure) of thermally treating a magnetic layer of a wafer, includes annealing, for a predetermined short duration, a magnetic layer of a single wafer.

Abstract: A method (and structure) of thermally treating a magnetic layer of a wafer, includes annealing, for a predetermined short duration, a magnetic layer of a single wafer.

Abstract: A method of thermally treating a magnetic layer of a wafer, includes annealing, for a predetermined short duration, a magnetic layer of a single wafer, applying at least one local magnetic field to the magnetic layer obtained without making electrical contact to the wafer, and cooling the single wafer using argon. The annealing includes heating only a local area on the single wafer at a temperature of 280 degrees C for 60 seconds in the presence of a magnetic field using a rapid thermal anneal (RTA) lamp. The applying a magnetic field to the magnetic layer is conducted after the annealing and ancludes applying local fields in different directions to different areas of the single wafer. The single wafer includes a magnetic stack formed thereon, the magnetic stcak having a structure of 50TaN/50Ta/175PtMn/15CoFe/9Al/50Py/100TaN.

Abstract: A method (and structure) of thermally treating a magnetic layer of a wafer, includes annealing, for a predetermined short duration, a magnetic layer of a single wafer.