Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.

Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.

Abstract: Automated analyzing of an endpoint report for a design of an electronic circuit is provided, which includes: identifying, by a processing device, that one or more test points of a selected path of the endpoint report are associated with one or more inverter devices of an inverter chain of the design of the electronic circuit; establishing, by the processing device, a chain criticality value for the inverter chain; and determining, by the processing device, whether to identify the inverter chain as a dispensable inverter chain, the determining using, at least in part, the chain criticality value for the inverter chain. The establishing may include updating the chain criticality value for each inverter device of the inverter chain, where the chain criticality value is a summed value obtained from criticality values for the one or more inverter devices of the inverter chain.

Abstract: A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

Abstract: Automated analyzing of an endpoint report for a design of an electronic circuit is provided, which includes: identifying, by a processing device, that one or more test points of a selected path of the endpoint report are associated with one or more inverter devices of an inverter chain of the design of the electronic circuit; establishing, by the processing device, a chain criticality value for the inverter chain; and determining, by the processing device, whether to identify the inverter chain as a dispensable inverter chain, the determining using, at least in part, the chain criticality value for the inverter chain. The establishing may include updating the chain criticality value for each inverter device of the inverter chain, where the chain criticality value is a summed value obtained from criticality values for the one or more inverter devices of the inverter chain.

Abstract: The invention relates to a current sense amplifier (103) comprising a reference current input terminal (109), a sense control line input terminal (125), a sense current input terminal (108), a first output terminal (106), and a second output terminal (107).

Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.

Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.

Abstract: An improved method for fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro comprises: Loading hardware design timing data to determine pins where an early mode slack fix can be applied to fix an early mode slack; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value.

Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.

Abstract: An improved method for fixing an early mode slack in a hierarchically designed hardware device with at least one source macro, an integration unit and at least one sink macro comprises: Loading hardware design timing data to determine pins where an early mode slack fix can be applied to fix an early mode slack; for each such pin determining a location across the design hierarchy for the early mode slack fix by calculating a weight value for each of a selection of fix locations of the early mode slack based on absolute values of arrival times of data signals, ratio and difference between arrival times of late mode data signals and early mode data signals; and assigning the early mode slack fix to the determined location based on said weight value.

Abstract: A method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, wherein the decimal operands are in hexadecimal sign magnitude format.

Abstract: Some example embodiments include an apparatus for comparing a first operand to a second operand. The apparatus includes a SIMD accelerator configured to compare first multiple parts (e.g., bytes) of first operand to second multiple parts (e.g., bytes) of the second operand. The SIMD accelerator includes a ones' complement subtraction logic and a twos' complement logic configured to perform logic operations on the multiple parts of the first operand and the multiple parts of the second operand to generate a group of carry out and propagate data across bits of the multiple parts. At least a portion of the group of carry out and propagate data is reused in the group of logic operations.

Abstract: A computer-readable storage storing instructions for a processor. Execution of the instructions causes loading unit timing data descriptive of an upper hierarchy. Execution of the instructions cause the loading of a unit timing path, and the loading of macro timing data into the memory. Execution of the instructions further cause the replacement of at least a portion of the unit timing report with the macro timing data, and computation of arrival times, slacks, and slews. Execution of the instructions also cause computation of path statistics in accordance with the arrival times, slacks and slews, and generation of a end point report for the unit timing path, including path statistics.

Abstract: A computer-readable storage storing instructions for a processor. Execution of the instructions causes loading unit timing data descriptive of an upper hierarchy. Execution of the instructions cause the loading of a unit timing path, and the loading of macro timing data into the memory. Execution of the instructions further cause the replacement of at least a portion of the unit timing report with the macro timing data, and computation of arrival times, slacks, and slews. Execution of the instructions also cause computation of path statistics in accordance with the arrival times, slacks and slews, and generation of a end point report for the unit timing path, including path statistics.

Abstract: A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results.