Abstract: Disclosed is an image segmenting device provided with a plurality of pixel pulsed artificial neurons which are coupled to each other via one respective weighted coupling. A weight-modifying unit modifies the weights of the couplings according to the pulse signals of the neurons such that neurons of a segment that is to be formed emit neuron pulse signals in an increasingly synchronous manner.

Abstract: Method and device for the exposure-dependent noise correction in images sensor which can be addressed in lines and columns are converted into digital values and an offset voltage correction is carried out by a summer, a gain correction is carried out by a multiplier, and an exposure-dependent dark current correction is carried out by a further summer. Further, the coefficients that depend on the line number, the column number and the integration time, are determined by linear approximations. As a result, the fixed pattern noise (PFN) in CMOS image sensor can be efficiently suppressed with a relatively low outlay.

Abstract: Defective pixels of an image sensor are corrected by the device having an interpolator, a defect column memory, and a switch that changing the output signal under the control of the defect column memory. Depending on a defect signal from the defect column memory, input pixel data are output as output pixel data in a defect-free case and pixel data interpolated from adjacent pixel data are output as output pixel data in a defect case. The defect signal is generated from an image line address and an image column address such that a pointer memory is addressed by the image line address, wherein the pointer memory contains a pointer for each of at least some of the image lines, the pointer addressing a defect column memory with column numbers stored therein of defective image columns. The column number is read from the defect column memory, the column number is compared with the column address, and the defect signal is formed from the comparison.

Abstract: The apparatus has a multiplicity of control modules which are assigned to a multiplicity of processing modules for driving purposes. These separate control modules are driven by a superordinate controller and are synchronized by a common synchronization unit on the basis of, by way of example, handshake lines and semaphores. The effect achieved by such an apparatus is that the transmission bandwidth between an external instruction memory and the large-scale integrated system can be reduced, and the total power loss can be lowered by intermittently disconnecting processing modules which are currently not needed. Furthermore, such an architecture supports the separate development of control programs for the individual control modules.

Abstract: The subject matter of the application essentially relates to a matrix array of processor units, each processor unit having, in addition to an arithmetic logic unit and a result register bank, a further arithmetic logic unit, a multiplier/adder unit, a storage unit of a distributed screen section buffer and a local general purpose memory. The processor is distinguished by a high processing speed in conjunction with a small chip area and enables real-time processing even in the case of computation-intensive image processing methods such as 2D convolution, Gabor transformation, Gaussian or Laplacian pyramids, block matching, DCT or MPEG2.

Abstract: Circuit arrangement for calculating matrix operations, such as those which recur frequently in signal processing, specifically in conjunction with neural networks, having a systolic array of multipliers and adders, downstream from which a recursive accumulator is connected. In addition to products, sums and differences of matrices, this circuit arrangement also allows squares, absolute magnitudes of sums and differences and squares of sums and differences of two matrices to be calculated very efficiently. Furthermore, with the aid of the recursive accumulator, it is possible to transpose matrices, to calculate row sums and column sums, and to search for minimum or maximum matrix elements.

Abstract: A digital neural network has a plurality of neurons (NR) completely meshed with one another, each of which comprises an evaluation stage having a plurality of evaluators (B) that is equal in number to the plurality of neurons (NR) and each of which comprises a decision stage having a decision unit (E). An adjustment information (INF.sub.E) that effects a defined pre-adjustment of the decision unit (E) can be supplied to every decision unit (E) by a pre-processing means via an information input. A weighting information (INF.sub.G) can be supplied to every evaluator (B) by a pre-processing means via an individual information input. An output information (INF.sub.A) can be output by every decision unit (E) to a post-processing means via a respective individual information output. The information outputs of the decision units (E) are each connected to an individual processing input of all evaluators (B) allocated to the appertaining decision unit (E).

Abstract: A network architecture for the programmable emulation of large artificial neural networks ANN having digital operation employs a plurality L of neuron units of identical structure, each equipped with m neurons, the inputs (E) thereof being connected to network inputs (E.sub.N) multiplied or branching via individual input registers (REG.sub.E). The outputs (A) of the neuron units are connectable to network outputs (A.sub.N) at different points in time via individual multiplexers (MUX) and individual output registers (REG.sub.A) and the neuron units have individual auxiliary inputs via which signals can be supplied to them that represent weighting values (W) for weighting the appertaining neural connections and represent thresholds (0) for weighting input signals.

Abstract: In discrete wafer-scale integration abbreviated as WSI, pre-tested chips are mounted and bonded on a pre-wired wafer. Silicon usually serves as the wafer substrate because the wafer wiring can be cost-beneficially produced with a standard multi-layer process. The conducting properties of such a wafer micro-wiring forbid the use of long leads given high timing clocks, so that intermediate drivers must be utilized. Previous solutions make use of separate driver chips that must be placed, bonded and tested in addition to the actual function chips. In the disclosed WSI system, the intermediate drivers are not realized as separate chips but are implemented on the function chip itself.

Abstract: A method and apparatus for the production of a test-compatible, largely defect-tolerant configuration of redundantly implemented, systolic VLSI systems. The method and apparatus for the configuration of redundantly implemented, systolic VLSI systems meets the conditions of defect-tolerance, test-compatibility and minimum hardware requirement. For this purpose, every module of the multi-dimensional systolic VLSI system has control logic allocated to it which controls A, B and C switches for the appertaining module. It is possible with the use of these switches to bridge a maximum of up to two faulty modules per row and one faulty module per column. A configuration algorithm provides a determination as to whether the established VLSI system is in the position to be able to execute the desired arithmetic operations.