Abstract: The invention relates to a test circuit configuration. Every gate terminal of a transistor to be tested is coupled to a gate voltage source in such a manner that the gate voltage can be measured and adjusted individually on every gate terminal. The source terminal of every transistor to be tested can be coupled to the source voltage source in such a manner that the source voltage can be measured and adjusted individually on every source terminal.

Abstract: An apparatus and method for testing a plurality of electrical components that are coupled to one another. Further, an electrical selection unit, coupled to the electrical components to be tested, is provided for selecting at least one electrical component to be tested. A parasitic voltage drop in the testing circuit can be at least partially compensated using a control element coupled to the electrical components to be tested. The invention makes it possible, for testing of electrical components on a wafer over a large distance, i.e., several millimeters, to permit automated compensation of interference influences which occur as a result of the lines coupling or connecting the components to be tested.

Abstract: The invention relates to an electric selection unit for selecting an electric component to be tested. The invention also relates to a control element by means of which parasitic voltage drop in the test circuit arrangement can be compensated for.

Abstract: The invention relates to a test circuit configuration. Every gate terminal of a transistor to be tested is coupled to a gate voltage source in such a manner that the gate voltage can be measured and adjusted individually on every gate terminal. The source terminal of every transistor to be tested can be coupled to the source voltage source in such a manner that the source voltage can be measured and adjusted individually on every source terminal.

Abstract: A power transistor has a plurality of contacted, individual transistors. The contacts of these individual transistors are arranged at such intervals from one another that a temperature distribution results during operation that is substantially uniform for an intended power range of the transistor.

Abstract: Power amplifier circuit for integrated digital circuits that combines the low permanent current consumption of a NOF push-pull output stage with the well-defined high level of a NON-NOFF amplifier stage having external clamp diode. An optimization of the leading edge is additionally achieved by fast drive and transient overdrive. A preceding inverter reduces the input capacitance of the overall circuit.

Abstract: Address amplifier circuit having automatic interlock and protection against multiple addressing for use in static GaAs RAMs. In the address amplifier circuit the address is doubly stored and only those signals that cannot trigger a misdecoding are forwarded from the address amplifier to a decoder circuit.