Abstract: An integrated multi-layer insulator memory cell is produced via silicon-gate technology, with self-adjusting, overlapping polysilicon contact wherein a gate oxide of a peripheral transistor is produced after the application of multi-layer insulating layer comprised of a storage layer and a "blocking" layer. The "blocking" layer consists of an oxynitride layer formed by oxidation of a silicon nitride layer surface or an additionally applied SiO.sub.2 layer and has a layer thickness of about 5 to 30 nm. Such "blocking" layer prevents an undesired injection of charge carriers from the silicon-gate electrode. It also provides means for forming a self-adjusting, overlapping polysilicon contact.

Abstract: An integratable semi-conductor memory cell has two bipolar transistors which are identical to one another and which have their collectors connected in series with respective circuit parts having a non-linear current characteristic, the respective circuit parts being connected to a first electrical potential. The circuit parts are also connected to the base of the other respective transistor. One emitter of each of the transistors is provided for control by means of logic signals and the invention is particularly characterized in that the circuit part located between the collector of each one of the transistors and a switching point carrying the first electrical potential are selected in such a fashion that the slope dU/dI of the current-voltage characteristic will always be higher than the slope of the corresponding current values in the current-voltage characteristic of the pn-junctions of the emitter-base circuit of both transistors.

Abstract: A process is disclosed for producing a high frequency transistor having a small emitter width. The high frequency transistor has a base zone consisting of an inactive region and of an active region. The lateral extension of the active region is determined by a "beak-shaped" portion of the insulation oxide. In order to permit the least possible number of process steps, the ion implanted base zone is not produced until the emitter window is opened. The invention is particularly suited for the production of integrated circuits.

Abstract: Semiconductor components, as for LSI-circuits are produced in such a manner that epitaxial layers as well as buried layers are dispensed with while an increased manufacturing yield and an increased structural packing density is achieved via an oxide insulating technique. The process involves applying and structuring a first insulating layer, such as composed of Si.sub.3 N.sub.4, onto a semiconductor substrate having a first zone of one conductivity type therein, etching insulating grooves into the substrate areas not covered with the first insulating layer and filling such grooves with a second insulating layer, such as composed of SiO.sub.2, which is thicker than the first insulating layer, and then emplacing the various semiconductor structures at select surface areas between spaced-apart areas of the second insulating layer so as to complete the semiconductor structure.

Abstract: A high-frequency transistor is provided having a small effective emitter width and a low base bulk resistance. The transistor is isolated from adjacent components by insulating material portions. The base zone comprises first and second doped zones. The first zone establishes the effective emitter width and has a lower concentration than the second zone. The lateral extent of the first zone is established by one of the insulating material portions and the second zone of the base zone. The collector of the transistor is positioned beneath both the first and second zones of the base zone and the emitter of the transistor is positioned above the first zone and an end portion of the second zone.

Abstract: A combination insulating means comprised of a pn-junction overlaid with a SiO.sub.2 filling within a groove is provided between IC elements in a monolithic semiconductor device. Such combination insulating means electrically and mechanically isolate at least two areas of a n-conductive surface zone, each of which supports an IC element. The n-conductive surface zone is supported on a p-conductive silicon base and the free surface of the n-conductive surface zone is coated with a Si.sub.3 N.sub.4 layer, which during the various fabrication steps of the monolithic semiconductor device protects coated areas of the n-conductive surface zone from etchants, oxidation and from dopants.

Abstract: A Si crystal substrate is orientated so that the 100-plane of the crystal lattice coincides with a surface thereof to be etched, and etch-resistant material such as composed of Si.sub.3 N.sub.4, Ta, etc. is coated onto selected areas of the surface to be etched and an etchant composed of a mixture containing for each 100 gr of HNO.sub.3, 20 gr of H.sub.2 O, 4 gr of HF and 110 gr of CH.sub.3 COOH is applied onto the surface to be etched for a period of time sufficient to produce a groove or recess having a relatively gradually sloped side wall in relation to the (100) surface being etched.