Patents by Inventor Ulrich Weigand

Ulrich Weigand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120198425
    Abstract: A compiler of a single instruction multiple data (SIMD) information handling system (IHS) identifies “if-then-else” statements that offer opportunity for conditional branch conversion. The compiler converts those “if-then-else” statements into “conditional branch and prepare” statements as well as “branch return” statements. The compiler compiles source code file information containing “if-then-else” statement opportunities into compiled code, namely an executable program. The SIMD IHS employs a processor or processors to execute the executable program. During execution, the processor generates and updates SIMD lane mask information to track and manage the conditional branch loops of the executing program. The processor saves branch addresses and employs SIMD lane masks to identify conditional branch loops with different branch conditions than previous conditional branch loops. The processor may reduce SIMD IHS processing time during processing of compiled code of the original “if-then-else” statements.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexandre E. Eichenberger, Brian Flachs, Dorit Nuzman, Ira Rosen, Ulrich Weigand, Ayal Zaks
  • Publication number: 20120023316
    Abstract: The illustrative embodiments comprise a method, data processing system, and computer program product having a processor unit for processing instructions with loops. A processor unit creates a first group of instructions having a first set of loops and second group of instructions having a second set of loops from the instructions. The first set of loops have a different order of parallel processing from the second set of loops. A processor unit processes the first group. The processor unit monitors terminations in the first set of loops during processing of the first group. The processor unit determines whether a number of terminations being monitored in the first set of loops is greater than a selectable number of terminations. In response to a determination that the number of terminations is greater than the selectable number of terminations, the processor unit ceases processing the first group and processes the second group.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Flachs, Charles R. Johns, Ulrich Weigand
  • Publication number: 20110320681
    Abstract: Memory management of processing systems running in a virtual computer environment and of processes running in an operating system environment includes identifying a usage pattern of a page in memory. The usage pattern is identified by tracking operations conducted with respect to the page. The memory management also includes designating the page as a candidate for sharing when the usage pattern reflects that a number of updates made to the page does not exceed a predefined threshold value. The candidate page is allocated to a first process or virtual machine. The memory management also includes sharing access to the candidate page with a second process or virtual machine when content in the candidate page matches content of page allocated for the second process or virtual machine to an address space of the candidate page.
    Type: Application
    Filed: June 28, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christian Borntraeger, Christian Ehrhardt, Carsten Otte, Martin Schwidefsky, Ulrich Weigand
  • Publication number: 20110145503
    Abstract: A method for computing includes executing a program, including multiple cacheable lines of executable code, on a processor having a software-managed cache. A run-time cache management routine running on the processor is used to assemble a profile of inter-line jumps occurring in the software-managed cache while executing the program. Based on the profile, an optimized layout of the lines in the code is computed, and the lines of the program are re-ordered in accordance with the optimized layout while continuing to execute the program.
    Type: Application
    Filed: December 16, 2009
    Publication date: June 16, 2011
    Applicant: International Business Machines Corporation
    Inventors: Revital Erez, Brian Flachs, Mark Richard Nutter, John Kevin Patrick O'Brien, Ulrich Weigand, Ayal Zaks
  • Patent number: 7506095
    Abstract: A method for providing execute-in-place functionality in a data processing system. In one embodiment, the method includes determining whether a file system driver that manages a file system containing a file provides a file system direct-access interface. Execute-in-place functionality is used in response to determining both that the file system driver provides the file system direct-access interface and that a device driver provides a device direct-access interface. The file system direct-access interface is used to provide the execute-in-place functionality in response to determining that the file system is configured to enable execute-in-place functionality.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: March 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Carsten Otte, Ulrich Weigand
  • Publication number: 20080127221
    Abstract: The present invention discloses an operating system which provides a new and inventive system and method for implementing the execute-in-place functionality.
    Type: Application
    Filed: April 4, 2006
    Publication date: May 29, 2008
    Inventors: Carsten Otte, Ulrich Weigand