Patents by Inventor Ulrike Bewersdorff-Sarlette

Ulrike Bewersdorff-Sarlette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230081559
    Abstract: A coating for planarization and stabilization of a laser-structured surface of an optoelectronic component, the optoelectronic component having a layer system including a first electrode, a second electrode, and at least one photoactive layer, wherein the at least one photoactive layer is disposed at least partly between the electrodes, and wherein the layer system is laser-structured, the coating including a polythiolene matrix, wherein the polythiolene matrix is formed by polymerization from at least one first monomer and one second monomer, wherein the first monomer is a polyfunctional thiol having at least three thiol groups, the second monomer is a polyfunctional alkene having at least two C—C double bonds, and the coating is disposed on the optoelectronic component and has at least partial direct contact with the layer system and/or diffusion contact with the layer system for at least the first monomer and/or the second monomer.
    Type: Application
    Filed: December 11, 2020
    Publication date: March 16, 2023
    Inventors: Ulrike Bewersdorff-Sarlette, Andre Weiss
  • Publication number: 20220310949
    Abstract: When organic photovoltaic components are laser-structured, protuberances occur, which can protrude significantly beyond the height of the layered stack. The invention describes a technique for stabilising the laser-structured protuberances so that further processing of the semi-finished product is possible, and describes the integration of said product in a subsequent encapsulation of the OPV component.
    Type: Application
    Filed: December 16, 2019
    Publication date: September 29, 2022
    Inventors: Ulrike BEWERSDORFF-SARLETTE, Martin PFEIFFER-JACOB, Michiel TOP, John FAHLTEICH, Nicole PRAGER
  • Patent number: 11355719
    Abstract: An optoelectronic component on a substrate includes a first and a second electrode. The first electrode is arranged on the substrate and the second electrode forms a counter electrode. At least one photoactive layer system is arranged between these electrodes. The at least one photoactive layer system including at least one donor-acceptor system having organic materials.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: June 7, 2022
    Assignee: HELIATEK GMBH
    Inventors: Martin Pfeiffer, Christian Uhrich, Ulrike Bewersdorff-Sarlette, Jan Meiss, Karl Leo, Moritz Riede, Sylvio Schubert, Lars Mueller-Meskamp
  • Patent number: 9418864
    Abstract: In one embodiment, a method of forming a semiconductor device is disclosed. A high-k dielectric is deposited of over a semiconductor body, and a portion of the high-k dielectric is wet etched an etchant selected from the group consisting of hot phos, piranha, and SC1.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Danny Pak-Chum Shum, Alfred Vater, John Power, Wolfram Langheinrich, Ulrike Bewersdorff-Sarlette
  • Publication number: 20150295195
    Abstract: An optoelectronic component on a substrate includes a first and a second electrode. The first electrode is arranged on the substrate and the second electrode forms a counter electrode. At least one photoactive layer system is arranged between these electrodes. The at least one photoactive layer system including at least one donor-acceptor system having organic materials.
    Type: Application
    Filed: July 2, 2013
    Publication date: October 15, 2015
    Applicant: HELIATEK GMBH
    Inventors: Martin PFEIFFER, Christian UHRICH, Ulrike BEWERSDORFF-SARLETTE, Jan MEISS, Karl LEO, Moritz RIEDE, Sylvio SCHUBERT, Lars MUELLER-MESKAMP
  • Patent number: 7678654
    Abstract: A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: March 16, 2010
    Assignee: Qimonda AG
    Inventors: Christoph Kleint, Clemens Fitz, Ulrike Bewersdorff-Sarlette, Christoph Ludwig, David Pritchard, Torsten Müller, Hocine Boubekeur
  • Publication number: 20090189280
    Abstract: In one embodiment, a method of forming a semiconductor device is disclosed. A high-k dielectric is deposited of over a semiconductor body, and a portion of the high-k dielectric is wet etched an etchant selected from the group consisting of hot phos, piranha, and SC1.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Inventors: Daniel Pak-Chum Shum, Alfred Vater, John Power, Wolfram Langheinrich, Ulrike Bewersdorff-Sarlette
  • Publication number: 20080002466
    Abstract: A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Christoph Kleint, Clemens Fitz, Ulrike Bewersdorff-Sarlette, Christoph Ludwig, David Pritchard, Torsten Muller, Hocine Boubekeur
  • Patent number: 6927154
    Abstract: A gate structure of a transistor is fabricated with an additional barrier formed on a metal layer of the gate structure before the deposition of a silicon oxide layer. Applying this barrier layer on the metal layer before the deposition of the silicon oxide layer prevents an oxidation of the metal during the deposition of the silicon oxide layer. A lowering of the conductivity of the metal layer or a loss of metal through sublimating metal oxide is thereby prevented. As a result, in particular the performance of the gate structure or of the transistor is improved further. In addition, disturbing coupling effects in the circuit are significantly reduced by the use of the silicon oxide cap.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: August 9, 2005
    Assignee: Infineon Technologies AG
    Inventors: Werner Graf, Ulrike Bewersdorff-Sarlette
  • Patent number: 6919269
    Abstract: A method for fabricating a semiconductor component includes: deposition of a polysilicon layer on a substrate, deposition of a precursor layer on the polysilicon layer, and deposition of a protective layer on the precursor layer. A crystalline transformation occurs in the precursor layer at a first temperature to form an electrode layer. The layers are patterned to form an electrode stack, and the polysilicon layer is oxidized at a second temperature such that no crystalline transformation occurs in the electrode layer.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: July 19, 2005
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Wolfgang Jäger, Ulrike Bewersdorff-Sarlette, Stephan Wege
  • Publication number: 20040150108
    Abstract: A microelectronic component is described having a barrier layer formed from WNx and a method is described for fabricating such a microelectronic component. The stoichiometry of the barrier formed from WNx is chosen such that 0.5>x>0.3 holds true. The barrier has a very high thermostability and also a low electrical resistance and is therefore suitable in particular for use in a gate stack.
    Type: Application
    Filed: December 1, 2003
    Publication date: August 5, 2004
    Inventors: Axel Buerke, Ulrike Bewersdorff-Sarlette
  • Publication number: 20040147102
    Abstract: The invention relates to a production method for a semiconductor component, with a substrate (1) and an electrode stack (7, 9′, 11′, 13), comprising a polysilicon electrode layer (7) and a tungsten-containing electrode layer (9′) arranged thereon.
    Type: Application
    Filed: November 14, 2003
    Publication date: July 29, 2004
    Inventors: Manfred Schneegans, Wolfgang Jager, Ulrike Bewersdorff-Sarlette, Stephan Wege
  • Publication number: 20030215986
    Abstract: A gate structure of a transistor is fabricated with an additional barrier formed on a metal layer of the gate structure before the deposition of a silicon oxide layer. Applying this barrier layer on the metal layer before the deposition of the silicon oxide layer prevents an oxidation of the metal during the deposition of the silicon oxide layer. A lowering of the conductivity of the metal layer or a loss of metal through sublimating metal oxide is thereby prevented. As a result, in particular the performance of the gate structure or of the transistor is improved further. In addition, disturbing coupling effects in the circuit are significantly reduced by the use of the silicon oxide cap.
    Type: Application
    Filed: May 6, 2003
    Publication date: November 20, 2003
    Inventors: Werner Graf, Ulrike Bewersdorff-Sarlette
  • Publication number: 20030082862
    Abstract: During the fabrication of patterned gate layer stacks for transistors in integrated semiconductor circuits, a lower and an upper gate layer are deposited. Both layers are patterned laterally. The lower gate layer made of polysilicon is oxidized to bind impurity ions that have indiffused near its sidewall spatially in an oxide. If the upper gate layer is composed of tungsten, the latter can be damaged during the oxidation and the conductivity of the gate layer stack can be reduced. Sidewall coverings deposited onto the upper gate layer before the oxidation also do not afford protection against a tungsten oxidation if the sidewall oxide grows from the side more deeply into the gate layer stack than as far as the inner sides of the sidewall coverings. The patterning of the lower gate layer is divided into two separate process steps between which the sidewall coverings are formed.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 1, 2003
    Inventors: Frank Richter, Ulrike Gruning-V. Schwerin, Ulrike Bewersdorff-Sarlette, Alexander Ruf