Abstract: An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line.

Abstract: An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line.

Abstract: A DRAM memory cell arrangement having memory cells each having a trench capacitor and a fin field-effect transistor or FinFET for addressing the trench capacitor. The memory cells are arranged in cell rows which are offset with respect to one another and are separated from one another by trench insulator structures. Word lines orthogonal to the cell rows mesh in comblike fashion between the cell rows and alternately traverse trench capacitors and channel regions of fin field-effect transistors. By means of a on-photolithographic mask having mask sections aligned with the trench capacitors, trench-insulator structures are provided in each case between a sidewall gate section of a word line and the adjoining trench capacitor, said trench-insulator structures decoupling the respective trench capacitor from the traversing word line.

Abstract: The invention relates to the fabrication of DRAM memory cell arrangements having fin field effect transistors and curved channel field effect transistors. The FinFETs and CFETs are formed in a manner oriented to semiconductor fins arranged in cell rows. Within the cell rows, the semiconductor fins are spaced apart from one another by cell insulator structures. Adjacent cell rows are spaced apart from one another by striplike trench insulator structures. The semiconductor fins are in each case recessed in one or in two inner trench sections by means of gate trenches which extend from a longitudinal side of the respective semiconductor fin to the opposite longitudinal side. By isotropically etching the oxide of the trench insulator structures, pockets (fin trenches) are formed, in a self-aligned manner with respect to the gate trenches in the trench insulator structures and filled with a gate conductor material.

Abstract: Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.

Abstract: A transistor structure having source/drain regions arranged in a horizontal plane along an x axis has a recess structure, which separates the two source/drain regions from one another and increases the effective channel length Leff of the transistor structure. A vertical gate electrode with respect to the horizontal plane extends along the x axis and in this case encloses an active zone of the transistor structure from two sides or completely. The effective channel width Weff is dependent on the depth to which the gate electrode is formed. A memory cell having a selection transistor in accordance with the transistor structure has both a low leakage current and a good switching behavior. By a suitable integration concept, the transistor structure is integrated into a memory cell array of a DRAM having hole trench capacitors or stacked capacitors.

Abstract: A description is given of a method for a selective masking of a structure with a small structure surface with respect to a structure with a larger structure surface. To that end, the structures are filled with a covering layer. The covering layer is formed with a larger thickness above the first structure, which has the larger structure surface, than above the second structure. Afterward, the covering layer is removed by a homogeneous removal method, so that first the structure surface of the second structure is uncovered. A simple self-aligning method for fabricating a mask for uncovering the second structure is thus provided.

Abstract: A memory cell field with an integrated arrangement of solid body electrolyte memory cells, and in particular of CBRAM solid body electrolyte memory cells with 1T1R architecture, wherein the solid body electrolyte memory cells each comprise a layer stack that comprises at least a bottom and a top electroconductive, in particular metal layer and a layer of solid body electrolyte material or ion conductor material, respectively, positioned therebetween, and wherein each solid body electrolyte memory cell can be controlled via a word line, a bit line, and a plate line by means of a selection transistor, wherein at least a number of solid body electrolyte memory cells in the memory cell field have a common plate electrode or are connected to a common plate line, respectively.

Abstract: A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.

Abstract: A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.

Abstract: An optical structure includes a substrate having semiconductor material and a grating structure. The grating structure has the property of emitting at least one frequency band so that light having a frequency from that frequency band cannot propagate in the grating structure. The grating structure has a configuration of pores and a defective region. The pores are disposed outside the defective region in a periodic array, and the periodic array is disturbed in the defective region. A surface of the grating structure is provided with a conductive layer at least in the vicinity of the defective region. A method for producing the optical structure is also provided.

Abstract: During the fabrication of patterned gate layer stacks for transistors in integrated semiconductor circuits, a lower and an upper gate layer are deposited. Both layers are patterned laterally. The lower gate layer made of polysilicon is oxidized to bind impurity ions that have indiffused near its sidewall spatially in an oxide. If the upper gate layer is composed of tungsten, the latter can be damaged during the oxidation and the conductivity of the gate layer stack can be reduced. Sidewall coverings deposited onto the upper gate layer before the oxidation also do not afford protection against a tungsten oxidation if the sidewall oxide grows from the side more deeply into the gate layer stack than as far as the inner sides of the sidewall coverings. The patterning of the lower gate layer is divided into two separate process steps between which the sidewall coverings are formed.

Abstract: A description is given of a method for a selective masking of a structure with a small structure surface with respect to a structure with a larger structure surface. To that end, the structures are filled with a covering layer. The covering layer is formed with a larger thickness above the first structure, which has the larger structure surface, than above the second structure. Afterward, the covering layer is removed by a homogeneous removal method, so that first the structure surface of the second structure is uncovered. A simple self-aligning method for fabricating a mask for uncovering the second structure is thus provided.

Abstract: An open form is produced with a plurality of in each case two-dimensionally structured layers. The form is made of silicon which is etchable in dependence on its doping. A first silicon layer is first produced, and a portion of the first layer which belongs to the form to be produced, is marked by doping at least one zone of the first layer. Subsequently, at least one further silicon layer is applied, and a portion belonging to the form is also marked therein. Finally, every unmarked portion of the layers is removed by etching depending on the respective doping of each layer. The open form is, in particular, a photonic crystal.

Abstract: An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

Abstract: In producing a silicon capacitor, hole structures (2) are created in a silicon substrate (1), at the surface of which structures a conductive zone (3) is created by doping and whose surface is provided with a dielectric layer (4) and a conductive layer (5), without filling the hole structures (2). To compensate mechanical strains upon the silicon substrate (1) which are effected by the doping of the conductive zone (3), a conformal auxiliary layer (6) is formed on the surface of the conductive layer (5), which auxiliary layer is under a compressive mechanical stress.

Abstract: For the operation of a memory cell arrangement with MOS transistors as memory cells that comprise a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric, whereby the silicon oxide layers are respectively at least 3 nm thick, a first cutoff voltage value is allocated to a first logical value and a second cutoff voltage value of the MOS transistor is allocated to a second logical value for storing digital data. The information stored in the memory cell can be modified by applying corresponding voltage levels, although a complete removal of charge stored in the silicon nitride layer is not possible because of the thickness of the silicon oxide layers. What is exploited when modifying the cutoff voltage is that the electrical field in the dielectric triple layer is distorted by charge stored in the silicon nitride layer.

Abstract: An optical structure which is suitable as an optical waveguide or cavity comprises a carrier having a lattice structure with a photonic band gap and a defect region. The lattice structure comprises pores which have constriction and are arranged in a periodic grid pattern which is disturbed in the defect region. The optical structure can be produced by the electrochemical etching of silicon.