Abstract: A semiconductor memory device suitable for use in a memory cell array includes a solid electrolyte memory cell including: a first electrode device, a second electrode device, and a solid electrolyte material region between the first and second electrode devices. The solid electrolyte material region is materially cohesive, and the second electrode device is materially cohesive.

Abstract: A method for producing trench DRAM cells, each having a trench capacitor and a fin field-effect transistor with a curved channel (CFET) for addressing the trench capacitor, is described. The memory cells are arranged in cell rows offset with respect to one another and are separated from one another by strip-like isolator structures. Buried word lines are embedded in the isolator structures and run along the longitudinal faces of semiconductor fins which are formed along the cell rows and include the active regions of the selection transistors. The internal electrodes of the trench capacitors are each connected with a low impedance via surface straps to first source/drain areas of the respective selection transistors. In one embodiment, one word line is formed for each isolator structure using an open bit line architecture, with only every alternate word line being used for addressing. A reinforced word line/trench isolator is provided between the word lines and the trench capacitors.