Patents by Inventor Uma Srinivasan
Uma Srinivasan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11657887Abstract: A method for testing a circuit includes performing, by a test engine, a test of bit write to a memory. The test includes defining a bit group based on a set of bits from an address of a memory location. The test further includes generating a bit mask for the bit group. The test further includes performing a bit write operation to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern. The test further includes reading content of the address. The test also includes comparing, using the bit mask, only bits corresponding to the bit group from the sequence of bits and from the content of the address.Type: GrantFiled: September 17, 2021Date of Patent: May 23, 2023Assignee: International Business Machines CorporationInventors: Thomas J. Knips, Uma Srinivasan, Daniel Rodko, Matthew Steven Hyde, William V. Huott
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Publication number: 20230089274Abstract: A method for testing a circuit includes performing, by a test engine, a test of bit write to a memory. The test includes defining a bit group based on a set of bits from an address of a memory location. The test further includes generating a bit mask for the bit group. The test further includes performing a bit write operation to the address to store a sequence of bits, the sequence of bits selected using a predetermined bit pattern. The test further includes reading content of the address. The test also includes comparing, using the bit mask, only bits corresponding to the bit group from the sequence of bits and from the content of the address.Type: ApplicationFiled: September 17, 2021Publication date: March 23, 2023Inventors: Thomas J. KNIPS, Uma SRINIVASAN, Daniel RODKO, Matthew Steven HYDE, William V. HUOTT
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Patent number: 11462295Abstract: A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.Type: GrantFiled: April 10, 2020Date of Patent: October 4, 2022Assignee: International Business Machines CorporationInventors: Timothy Meehan, Kirk D. Peterson, John B. DeForge, William V. Huott, Uma Srinivasan, Hyong Uk Kim, Michelle E. Finnefrock, Daniel Rodko
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Patent number: 11150971Abstract: Pattern recognition is used to proactively treat defects of repeating circuit topologies. A component of a computing environment is monitored for failures. The component includes one or more repeating circuit topologies. A determination is made as to whether a new failure within a repeating circuit topology of the one or more repeating circuit topologies has occurred within a predefined amount of time from a previous failure matching a selected pattern, in which the selected pattern indicates a non-contiguous growing defect. Based on determining the new failure has occurred within the predefined amount of time from the previous failure matching the selected pattern, corrective action for the component is proactively taken.Type: GrantFiled: April 7, 2020Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uma Srinivasan, K. Paul Muller, Kevin W. Kark, Pamela Antal
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Publication number: 20210319845Abstract: A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.Type: ApplicationFiled: April 10, 2020Publication date: October 14, 2021Inventors: Timothy MEEHAN, Kirk D. PETERSON, John B. DEFORGE, William V. HUOTT, Uma SRINIVASAN, Hyong Uk KIM, Michelle E. Finnefrock, Daniel RODKO
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Publication number: 20210311814Abstract: Pattern recognition is used to proactively treat defects of repeating circuit topologies. A component of a computing environment is monitored for failures. The component includes one or more repeating circuit topologies. A determination is made as to whether a new failure within a repeating circuit topology of the one or more repeating circuit topologies has occurred within a predefined amount of time from a previous failure matching a selected pattern, in which the selected pattern indicates a non-contiguous growing defect. Based on determining the new failure has occurred within the predefined amount of time from the previous failure matching the selected pattern, corrective action for the component is proactively taken.Type: ApplicationFiled: April 7, 2020Publication date: October 7, 2021Inventors: Uma Srinivasan, K. Paul Muller, Kevin W. Kark, Pamela Antal
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Patent number: 11081202Abstract: A computer-implemented method includes receiving a memory address of a memory location in a memory that has been identified to be failing. The method further includes determining that the memory location is from a particular portion of the memory. The method further includes, in response to a number of memory locations that are identified to be failing from the particular portion of the memory being below a predetermined threshold, logging the memory address in a set of failing address registers associated with the memory, otherwise, skipping the logging of the memory address in the failing address registers.Type: GrantFiled: October 1, 2019Date of Patent: August 3, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uma Srinivasan, Thomas J. Knips, Gregory J. Fredeman, Matthew Steven Hyde, Thomas E. Miller
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Patent number: 11069422Abstract: A method for testing a circuit includes performing, by a test engine, a test of a memory element of the circuit, the test accesses a memory location in the memory element, the memory location is identified by an address, and the memory location is accessed via a first port associated with a first port select bit. The method further includes, in response to detecting a failure associated with the memory location, determining an existing entry for the address in a failed address register, and determining that the existing entry in the failed address register is associated with a second port select bit, distinct from the first port select bit. The method further includes, in response to the second port select bit being distinct from the first port select bit, setting a multi-port failure flag for the memory element that is being tested.Type: GrantFiled: July 7, 2020Date of Patent: July 20, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew Steven Hyde, Uma Srinivasan, Thomas J. Knips, Gregory J. Fredeman
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Publication number: 20210098069Abstract: A computer-implemented method includes receiving a memory address of a memory location in a memory that has been identified to be failing. The method further includes determining that the memory location is from a particular portion of the memory.Type: ApplicationFiled: October 1, 2019Publication date: April 1, 2021Inventors: UMA SRINIVASAN, THOMAS J. KNIPS, GREGORY J. FREDEMAN, MATTHEW STEVEN HYDE, THOMAS E. MILLER
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Patent number: 10901818Abstract: Embodiments of the invention are directed to systems and methods for common request processing by a request formatting platform. The request formatting platform generates formatted requests for request processors according to specifications of a common request processing application programming interface (API). The same common request processing API is used by the request formatting platform to communicate with all of the request processors according to one particular format.Type: GrantFiled: June 28, 2019Date of Patent: January 26, 2021Assignee: Visa International Service AssociationInventors: Rohit Sukhija, Man Grace Wu, Jan Tore Klepp, Rajiv Dutta, Ghanshyam Rokde, Soorej Nair, Uma Srinivasan, Nathan Morgan, Sanjib Sengupta, Palaniappan Kathiresan
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Publication number: 20200409775Abstract: Embodiments of the invention are directed to systems and methods for common request processing by a request formatting platform. The request formatting platform generates formatted requests for request processors according to specifications of a common request processing application programming interface (API). The same common request processing API is used by the request formatting platform to communicate with all of the request processors according to one particular format.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: Rohit Sukhija, Man Grace Wu, Jan Tore Klepp, Rajiv Dutta, Ghanshyam Rokde, Soorej Nair, Uma Srinivasan, Nathan Morgan, Sanjib Sengupta, Palaniappan Kathiresan
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Patent number: 10402176Abstract: Methods, apparatus, systems and articles of manufacture to compiler compile code to generate dataflow code are described. An example compiler apparatus includes an intermediate representation transformer to transform input software code to intermediate representation code; an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and a target machine transformer to: convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and allocate registers within the dataflow intermediate representation code.Type: GrantFiled: December 27, 2017Date of Patent: September 3, 2019Assignee: Intel CorporationInventors: Kent Glossop, Kermin Fleming, Yongzhi Zhang, Simon Steely, Jr., Jim Sukha, Uma Srinivasan
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Patent number: 10387146Abstract: Embodiments of the invention are directed to systems and methods for common request processing by a request formatting platform. The request formatting platform generates formatted requests for request processors according to specifications of a common request processing application programming interface (API). The same common request processing API is used by the request formatting platform to communicate with all of the request processors according to one particular format.Type: GrantFiled: November 18, 2016Date of Patent: August 20, 2019Assignee: Visa International Service AssociationInventors: Rohit Sukhija, Man Grace Wu, Jan Tore Klepp, Rajiv Dutta, Ghanshyam Rokde, Soorej Nair, Uma Srinivasan, Nathan Morgan, Sanjib Sengupta, Palaniappan Kathiresan
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Patent number: 10373678Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.Type: GrantFiled: November 30, 2017Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: William V. Huott, Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu
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Patent number: 10332591Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.Type: GrantFiled: February 22, 2018Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: William V. Huott, Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu
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Publication number: 20190042217Abstract: Methods, apparatus, systems and articles of manufacture to compiler compile code to generate dataflow code are described. An example compiler apparatus includes an intermediate representation transformer to transform input software code to intermediate representation code; an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and a target machine transformer to: convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and allocate registers within the dataflow intermediate representation code.Type: ApplicationFiled: December 27, 2017Publication date: February 7, 2019Inventors: Kent Glossop, Kermin Fleming, Yongzhi Zhang, Simon Steely, JR., James Sukha, Uma Srinivasan
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Patent number: 10163493Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.Type: GrantFiled: May 8, 2017Date of Patent: December 25, 2018Assignee: International Business Machines CorporationInventors: William V. Huott, Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu
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Publication number: 20180322917Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.Type: ApplicationFiled: February 22, 2018Publication date: November 8, 2018Inventors: William V. Huott, Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu
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Publication number: 20180322916Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.Type: ApplicationFiled: November 30, 2017Publication date: November 8, 2018Inventors: William V. Huott, Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu
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Publication number: 20180322915Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.Type: ApplicationFiled: May 8, 2017Publication date: November 8, 2018Inventors: William V. Huott, Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu