Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: An array of memory cells includes a layer of nonpatterned storage material, in accordance with embodiment. In one embodiment, a circuit includes an array of memory cells. The array of memory cells includes first conductive electrodes. The array includes a layer of storage material including a nonpatterned region disposed over the first conductive electrodes. The array includes second conductive electrodes disposed over the nonpatterned region of the storage material. A given memory cell of the array is located where one of the second conductive electrodes overlaps one of the first conductive electrodes across the nonpatterned region of storage material.

Abstract: Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region of the semiconductor substrate recessed from the first region. The methods include forming a metal that is common to both the memory cells and the gate structures.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region of the semiconductor substrate recessed from the first region. The methods include forming a metal that is common to both the memory cells and the gate structures.

Abstract: Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a charge trap NAND flash memory device.

Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

Abstract: A semiconductor device structure and method to form the same. The semiconductor device structure includes a non-volatile charge trap memory device and a resistor or capacitor. A dielectric layer of a charge trap dielectric stack of the memory device is patterned to expose a portion of a first conductive layer peripheral to the memory device. A second conductive layer formed over the dielectric layer and on the exposed portion of the first conductive layer is patterned to form resistor or capacitor contacts and capacitor plates.

Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.