Abstract: A digital demodulator of data signals transmitted by linear amplitude modulation of a carrier, sampled under the control of clock pulses CK1, comprises an interpolating unit UIN including a tapped delay line TDL whose outputs carry, at a given instant, respective signal samples received during different clock cycles. These signal samples are fed to a transversal filter FIN also receiving two sets of interpolation coefficients a.sub.k, b.sub.k read out from respective memory sections ME1, ME2. The signal samples from the several delay-line taps are multiplied in filter FIN by the two sets of coefficients a.sub.k and b.sub.k, under the control of a pulse train CK2 and another pulse train CK3 of the same cadence but phase-shifted with reference to the former, and the two sets of resulting products are respectively summed in a digital adder SM and alternately read out to a phase corrector CJ recovering the phase coherence of the demodulated baseband signal.

Abstract: Digital signals asymmetrically modulated upon a carrier, with suppressed or vestigial second sideband, are recovered at a receiver by pseudo-coherent demodulation or periodic sampling and subsequent digitization to provide a train of raw data signals X from which a train of raw quadrature signals Y is derived by digital filtration. Signals X and Y are fed to a phase corrector where they are cross-multiplied with a sine function and a cosine function of a feedback signal W, approximating a corrective phase angle .phi.(t), to yield a corrected in-phase signal X' and a corrected quadrature signal Y'. Signal X' is quantized to provide a reference signal c which, upon subtraction from signal X', produces a bipolar difference signal whose sign bit is multiplied with either the entire signal Y' or its sign bit to provide an error signal V.