Patents by Inventor Umesh Kumar Mishra
Umesh Kumar Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10109713Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.Type: GrantFiled: September 30, 2016Date of Patent: October 23, 2018Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, CREE INC.Inventors: Alessandro Chini, Umesh Kumar Mishra, Primit Parikh, Yifeng Wu
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Publication number: 20170025506Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.Type: ApplicationFiled: September 30, 2016Publication date: January 26, 2017Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, Cree, Inc.Inventors: Alessandro Chini, Umesh Kumar Mishra, Primit Parikh, Yifeng Wu
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Patent number: 8147659Abstract: A gated electrode structure for altering a potential and electric field in an electrolyte near at least one working electrode is disclosed. The gated electrode structure may comprise a gate electrode biased appropriately with respect to a working electrode. Applying an appropriate static or dynamic (time varying) gate potential relative to the working electrode modifies the electric potential and field in an interfacial region between the working electrode and the electrolyte, and increases electron emission to and from states in the electrolyte, thereby facilitating an electrochemical, electrolytic or electrosynthetic reaction and reducing electrode overvoltage/overpotential.Type: GrantFiled: November 20, 2007Date of Patent: April 3, 2012Assignee: The Regents of the University of CaliforniaInventors: Rakesh K. Lal, Likun Shen, Umesh Kumar Mishra
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Publication number: 20110062449Abstract: A method for growth and fabrication of semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga, Al, In, B)N template or nucleation layer on the substrate, and growing the semipolar (Ga, Al, In, B)N thin films, heterostructures or devices on the planar semipolar (Ga, Al, In, B)N template or nucleation layer. The method results in a large area of the semipolar (Ga, Al, In, B)N thin films, heterostructures, and devices being parallel to the substrate surface.Type: ApplicationFiled: November 23, 2010Publication date: March 17, 2011Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Robert M. Farrell, JR., Troy J. Baker, Arpan Chakraborty, Benjamin A. Haskell, P. Morgan Pattison, Rajat Sharma, Umesh Kumar Mishra, Steven P. DenBaars, James S. Speck, Shuji Nakamura
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Patent number: 7846757Abstract: A method for growth and fabrication of semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices, comprising identifying desired material properties for a particular device application, selecting a semipolar growth orientation based on the desired material properties, selecting a suitable substrate for growth of the selected semipolar growth orientation, growing a planar semipolar (Ga,Al,In,B)N template or nucleation layer on the substrate, and growing the semipolar (Ga,Al,In,B)N thin films, heterostructures or devices on the planar semipolar (Ga,Al,In,B)N template or nucleation layer. The method results in a large area of the semipolar (Ga,Al,In,B)N thin films, heterostructures, and devices being parallel to the substrate surface.Type: GrantFiled: June 1, 2006Date of Patent: December 7, 2010Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: Robert M. Farrell, Jr., Troy J. Baker, Arpan Chakraborty, Benjamin A. Haskell, P. Morgan Pattison, Rajat Sharma, Umesh Kumar Mishra, Steven P. DenBaars, James S. Speck, Shuji Nakamura
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Patent number: 7700973Abstract: A dispersion-free high electron mobility transistor (HEMT), comprised of a substrate; a semi-insulating buffer layer, comprised of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), deposited on the substrate, an AlGaN barrier layer, with an aluminum (Al) mole fraction larger than that of the semi-insulating buffer layer, deposited on the semi-insulating buffer layer, an n-type doped graded AlGaN layer deposited on the AlGaN barrier layer, wherein an Al mole fraction is decreased from a bottom of the n-type doped graded AlGaN layer to a top of the n-type doped graded AlGaN layer, and a cap layer, comprised of GaN or AlGaN with an Al mole fraction smaller than that of the AlGaN barrier layer, deposited on the n-type doped graded AlGaN layer.Type: GrantFiled: October 12, 2004Date of Patent: April 20, 2010Assignee: The Regents of the University of CaliforniaInventors: Likun Shen, Sten Johan Heikman, Umesh Kumar Mishra
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Patent number: 7566580Abstract: Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (?m sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible.Type: GrantFiled: September 14, 2007Date of Patent: July 28, 2009Assignee: The Regents of the University of CaliforniaInventors: Stacia Keller, Umesh Kumar Mishra, Nicholas A. Fichtenbaum
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Publication number: 20090146162Abstract: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.Type: ApplicationFiled: February 12, 2009Publication date: June 11, 2009Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Arpan Chakraborty, Benjamin A. Haskell, Stacia Keller, James Stephen Speck, Steven P. DenBaars, Shuji Nakamura, Umesh Kumar Mishra
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Publication number: 20080113496Abstract: Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (?m sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible.Type: ApplicationFiled: September 14, 2007Publication date: May 15, 2008Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Stacia Keller, Umesh Kumar Mishra, Nicholas A. Fichtenbaum
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Patent number: 7186302Abstract: A method for the fabrication of nonpolar indium gallium nitride (InGaN) films as well as nonpolar InGaN-containing device structures using metalorganic chemical vapor deposition (MOVCD). The method is used to fabricate nonpolar InGaN/GaN violet and near-ultraviolet light emitting diodes and laser diodes.Type: GrantFiled: May 6, 2005Date of Patent: March 6, 2007Assignees: The Regents of the University of California, The Agency of Industrial Science and TechnologyInventors: Arpan Chakraborty, Benjamin A. Haskell, Stacia Keller, James Stephen Speck, Steven P. Denbaars, Shuji Nakamura, Umesh Kumar Mishra
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Patent number: 6610144Abstract: The present invention discloses a semiconductor film having a reduced dislocation density. The film comprises at least one interlayer structure, including a group III-nitride layer, a passivation interlayer disposed on the group III-nitride layer, interrupting the group III-nitride layer, and an island growth interlayer disposed on the passivation interlayer, and interrupting the group III-nitride layer. A method of making a semiconductor film of the present invention comprises producing a semiconductor film including at least one interlayer structure, each interlayer structure produced by the substeps of growing a group III-nitride layer, depositing a passivation interlayer on the group III-nitride layer, depositing an island growth interlayer on the passivation interlayer and continuing growing the group III-nitride layer.Type: GrantFiled: July 19, 2001Date of Patent: August 26, 2003Assignee: The Regents of the University of CaliforniaInventors: Umesh Kumar Mishra, Stacia Keller
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Publication number: 20020069817Abstract: The present invention discloses a semiconductor film having a reduced dislocation density. The film comprises at least one interlayer structure, including a group III-nitride layer, a passivation interlayer disposed on the group III-nitride layer, interrupting the group III-nitride layer, and an island growth interlayer disposed on the passivation interlayer, and interrupting the group III-nitride layer. A method of making a semiconductor film of the present invention comprises producing a semiconductor film including at least one interlayer structure, each interlayer structure produced by the substeps of growing a group III-nitride layer, depositing a passivation interlayer on the group III-nitride layer, depositing an island growth interlayer on the passivation interlayer and continuing growing the group III-nitride layer.Type: ApplicationFiled: July 19, 2001Publication date: June 13, 2002Inventors: Umesh Kumar Mishra, Stacia Keller
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Patent number: 6261931Abstract: A method for growing high-quality gallium nitride over a substrate is disclosed. The method comprises growing first layer with a high dislocation density over the substrate, a second layer having a high number of point defects and a reduced dislocation density as compared to the dislocation density of the first layer over the first layer, and a third layer having a reduced number of point defects as compared to the second layer over the second layer. The resulting gallium nitride is semi-insulating, which inhibits parasitic current flow and parasitic capacitive effects, yet it not so insulating that electron flow in adjacent transistor channels is inhibited.Type: GrantFiled: June 19, 1998Date of Patent: July 17, 2001Assignee: The Regents of the University of CaliforniaInventors: Stacia Keller, Bernd Peter Keller, Umesh Kumar Mishra, Steven P. DenBaars
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Patent number: 5872031Abstract: The present invention discloses a method of forming an oxide layer on a layer of gallium arsenide, including the steps of depositing a layer of aluminum arsenide on the layer of gallium arsenide, of exposing the layer of aluminum arsenide to an oxidizing gas mixture so that the aluminum arsenide is oxidized to aluminum oxide, and of controlling excess arsenic released in the aluminum oxide during the exposing step, so as to ensure enhanced electrical properties in the aluminum oxide. The method is used to provide an insulating gate layer for a GaAs field effect transistor by forming an oxide layer on GaAs and controlling excess arsenic so as to maintain high resistivity in the oxide layer and to avoid the formation of interface surface states which degrade transistor performance. The method is also used to provide complementary metal-insulator-semiconductor logic devices based on the gallium arsenide field effect transistor.Type: GrantFiled: November 27, 1996Date of Patent: February 16, 1999Assignee: The Regents of the University of CaliforniaInventors: Umesh Kumar Mishra, Primit A. Parikh
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Patent number: 5798555Abstract: The present invention discloses a method of forming an oxide layer on a layer of germanium including the steps of depositing a layer of aluminum arsenide on the layer of germanium, of exposing the layer of aluminum arsenide to an oxidizing gas mixture so that the aluminum arsenide is oxidized to aluminum oxide, and of controlling excess arsenic released in the aluminum oxide by the exposing step, so as to ensure enhanced electrical properties in the aluminum oxide. The method is used to provide an insulating gate layer for a Ge field effect transistor by forming an oxide layer on Ge and controlling excess arsenic so as to maintain high resistivity in the oxide layer and to avoid the formation of interface surface states which degrade transistor performance. The method is also used to provide complementary metal-insulator-semiconductor logic devices based on the germanium field effect transistor.Type: GrantFiled: November 27, 1996Date of Patent: August 25, 1998Assignee: The Regents of the University of CaliforniaInventors: Umesh Kumar Mishra, Steven P. DenBaars
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Patent number: 5795798Abstract: A method and apparatus for producing full-color luminescent monolithic semiconductor devices. Each portion of the device is bandgap engineered by using different dopants to change the direct bandgap of selected areas of each region, thereby allowing that region to produce different wavelengths of emitted light at high efficiencies.Type: GrantFiled: November 27, 1996Date of Patent: August 18, 1998Assignee: The Regents of the University of CaliforniaInventors: Umesh Kumar Mishra, Steven P. DenBaars, David Joseph Kapolnek
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Patent number: 5780355Abstract: A method for producing Group III nitride films with high indium content and superior optical quality. The Group III nitride film will produce light in the ultraviolet, blue, green, yellow, and red spectral regions. This will enable fabrication of full-color displays and produce a reliable white light source. A metal organic chemical vapor deposition (MOCVD) process in combination with a photochemical process reduces the growth temperature required to produce optical quality Group III nitride films.Type: GrantFiled: November 27, 1996Date of Patent: July 14, 1998Assignee: The Regents of the University of CaliforniaInventors: Umesh Kumar Mishra, Steven P. DenBaars, Stacia Keller
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Patent number: 5780922Abstract: A germanium-based field effect transistor has a passivation layer of aluminum oxide below a germanium channel and aluminum oxide gate oxide layer formed over the channel. The aluminum oxide layers are treated to reduce the density of surface state impurities, particularly arsenic released in the oxide layer as a result of forming the oxide layer. The low surface state germanium channel has very low phase noise and is suitable for use as a local oscillator in a heterodyne receiver.Type: GrantFiled: November 27, 1996Date of Patent: July 14, 1998Assignee: The Regents of the University of CaliforniaInventors: Umesh Kumar Mishra, Steven P. DenBaars
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Patent number: 5747838Abstract: A gallium arsenide-based field effect transistor has a passivation layer of aluminum oxide below a gallium arsenide channel and aluminum oxide gate oxide layer formed over the channel. The aluminum oxide layers are treated to reduce the density of surface state impurities, particularly arsenic released in the oxide layer as a result of forming the oxide layer. The low surface state gallium arsenide channel has very low phase noise and is suitable for use as a local oscillator in a heterodyne receiver.Type: GrantFiled: November 27, 1996Date of Patent: May 5, 1998Assignee: The Regents of the University of CaliforniaInventors: Umesh Kumar Mishra, Steven P. DenBaars