Patents by Inventor Umesh Nair

Umesh Nair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Timing convergence, efficient algorithm to automate swapping of standard devices with low threshold-voltage devices
    Patent number: 7254795
    Abstract: A method for optimizing low threshold-voltage (Vt) devices in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing timing violations, inserting low Vt devices at particular nodes of the integrated circuit design, and repeating the calculated possible solutions wherein choosing a solution and inserting low Vt devices at particular nodes to address timing violations within the integrated circuit design.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: August 7, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Umesh Nair, Toshinari Takayanagi
  • Timing convergence, efficient algorithm to automate swapping of standard devices with low threshold-voltage devices
    Publication number: 20060031799
    Abstract: A method for optimizing low threshold-voltage (Vt) devices in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing timing violations, inserting low Vt devices at particular nodes of the integrated circuit design, and repeating the calculated possible solutions wherein choosing a solution and inserting low Vt devices at particular nodes to address timing violations within the integrated circuit design.
    Type: Application
    Filed: June 15, 2005
    Publication date: February 9, 2006
    Inventors: Umesh Nair, Toshinari Takayanagi
  • System for optimizing buffers in integrated circuit design timing fixes
    Patent number: 6910197
    Abstract: A method for optimizing buffers in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing timing violations, inserting buffers at particular nodes of the integrated circuit design, and repeating the calculated possible solutions wherein choosing a solution and inserting buffers at particular nodes to address timing violations are within the integrated circuit design.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: June 21, 2005
    Assignee: Sun Microsystems, Inc.
    Inventor: Umesh Nair
  • Timing verification, automated multicycle generation and verification
    Publication number: 20050097487
    Abstract: A method for generating consistent functional and timing definitions. The method includes providing a common source description, the common source description corresponding to multicycle paths in an integrated circuit chip design, transforming the common source description to a functional definition, monitoring a functional simulation of the integrated circuit chip design using the functional definition, transforming the common source description to a timing definition, and performing a timing analysis of the integrated circuit chip design using the timing definition.
    Type: Application
    Filed: November 5, 2003
    Publication date: May 5, 2005
    Inventors: Mogens Lauritzen, Gaurav Garg, Umesh Nair
  • System for optimizing buffers in integrated circuit design timing fixes
    Publication number: 20040261046
    Abstract: A method for optimizing buffers in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing timing violations, inserting buffers at particular nodes of the integrated circuit design, and repeating the calculated possible solutions wherein choosing a solution and inserting buffers at particular nodes to address timing violations are within the integrated circuit design.
    Type: Application
    Filed: June 20, 2003
    Publication date: December 23, 2004
    Inventor: Umesh Nair