Abstract: Various techniques are provided to reduce shading in thermal images. In one example, a method includes receiving a captured thermal image having an original resolution, wherein the captured thermal image comprises scene information and shading information. The method includes processing the captured thermal image to generate a plurality of downscaled images each having an associated reduced resolution lower than the original resolution and different from each other, wherein the downscaled images exhibit reduced scene information in relation to the captured thermal image. The method includes generating a shading image using the downscaled images. The method includes adjusting the captured thermal image using the shading image to generate a processed thermal image with reduced shading information in relation to the captured thermal image. Additional methods and systems are also provided.

Abstract: Methods and systems for dynamically controlling buffer size in a computing device in a computing device (“PCD”) are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a first buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.

Abstract: Systems, methods, and computer programs are disclosed for dynamically adjusting memory channel interleave granularity. An embodiment of a system comprises a plurality of memory clients, a memory management unit (MMU), and an address translator. The plurality of memory clients are electrically coupled to each of a plurality of memory channels via an interconnect. The MMU is configured to receive a request for a memory allocation request for one or more memory pages from one of the plurality of memory client and, in response, select one of a plurality of interleave granularities for the one or more memory pages. The address translator is configured to translate a physical address to interleave memory data associated with the one or more memory pages at the selected interleave granularity.

Abstract: Systems, methods, and computer programs are disclosed for dynamically adjusting memory channel interleave granularity. An embodiment of a system comprises a plurality of memory clients, a memory management unit (MMU), and an address translator. The plurality of memory clients are electrically coupled to each of a plurality of memory channels via an interconnect. The MMU is configured to receive a request for a memory allocation request for one or more memory pages from one of the plurality of memory client and, in response, select one of a plurality of interleave granularities for the one or more memory pages. The address translator is configured to translate a physical address to interleave memory data associated with the one or more memory pages at the selected interleave granularity.

Abstract: Methods and systems for dynamically controlling buffer size in a computing device in a computing device (“PCD”) are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a fist buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.

Abstract: Systems and method are directed to reducing power consumption of a memory based on enabling partial page access. Based on system conditions such as operating frequency, access size for one or more memory access requests are determined. The access size is programmed in a mode register of the memory and one or more commands are issued for accessing the memory based on the programmed access size. Alternatively, the access sizes are specified within the one or more commands issued to the memory for accessing partial pages. Activating only the portion of a page corresponding to the partial page access reduces power consumption.

Abstract: Systems and method are directed to reducing power consumption and/or improving performance of a processing system comprising a processor subsystem and a memory subsystem. A variable length column command is used in place of a plurality of column commands directed to a same page of a memory bank of the memory subsystem. The variable length column command is provided to the memory subsystem based on a detection of a plurality of accesses directed to the same page.

Abstract: An integrated circuit is provided with a memory controller coupled to a buffered command and address bus and a pipelined data bus having a pipeline delay. The memory controller is configured to control the write and read operations for an external memory having a write latency period requirement. The memory controller is further configured to launch write data into the pipelined data bus responsive to the expiration of a modified write latency period that is shorter than the write latency period.

Abstract: The invention provides certain quinoxalines and aza-quinoxalines of the Formula (I), and their pharmaceutically acceptable salts, wherein J1, J2, R1, R2, R3, R22, Ra, Rb, Rc, Rd, X, Y, b, n, and q are as defined herein. The invention also provides pharmaceutical compositions comprising such compounds, and methods of using the compounds for treating diseases or conditions associated with uncontrolled or inappropriate stimulation of CRTH2 function.

Abstract: A method of classifying pixels in an image is described that includes calculating for each target pixel in the image, a functional value based on a median value of a block of pixels including the target pixel and storing the functional value for each pixel. Pixels in the image are then analyzed to determine if they correspond to edges in the image and if so, are classified as edge pixels. Next the stored functional values are analyzed to define a flat area delimiting function for the image. The stored functional values that do not correspond to edge pixels are then analyzed to define an image detail delimiting function and the non-flat area pixels are classified as being either flat area pixels or detail pixels based on the flat area delimiting function and the detail delimiting function.

Abstract: An image filter and method of smoothing pixel values. A pixel value of a pixel to be smoothed is compared with block average pixel values of each of a plurality of pixel blocks. The pixel to be smoothed may be downstream from each of the pixel blocks. If the difference between the pixel value and each of the block average pixel values is less than a corresponding sigma threshold value for each of the pixel blocks, a first sigma filter utilizing the block average pixel values is applied to the pixel to be smoothed. If the difference between the pixel value and any one of the block average pixel values is not less than a corresponding sigma threshold value, a second sigma filter is applied to the pixel to be smoothed.

Abstract: The invention provides certain quinoxalines and aza-quinoxalines of the Formula (I), and their pharmaceutically acceptable salts, wherein J1, J2, R1, R2, R3, R22, Ra, Rb, Rc, Rd, X, Y, b, n, and q are as defined herein. The invention also provides pharmaceutical compositions comprising such compounds, and methods of using the compounds for treating diseases or conditions associated with uncontrolled or inappropriate stimulation of CRTH2 function.

Abstract: A method of classifying pixels in an image is described that includes calculating for each target pixel in the image, a functional value based on a median value of a block of pixels including the target pixel and storing the functional value for each pixel. Pixels in the image are then analyzed to determine if they correspond to edges in the image and if so, are classified as edge pixels. Next the stored functional values are analyzed to define a flat area delimiting function for the image. The stored functional values that do not correspond to edge pixels are then analyzed to define an image detail delimiting function and the non-flat area pixels are classified as being either flat area pixels or detail pixels based on the flat area delimiting function and the detail delimiting function.

Abstract: A cash management safe includes a bill validator and stacker and a bagging mechanism for sealing received bills in a tamper evident bag prior to allowing the safe to be opened. Deposited bills are sealed in the bag upon expiration of a predetermined accumulation period, when an unlock code is entered in the safe's door lock, or when the capacity of the bag has been reached. The bag is sealed and die contents reported to a remote cash management server prior to unlocking the safe door, to reduce opportunities for loss during cash handling and transport.

Abstract: An oral solid dosage form having improved dissolution profile and a method of producing the same are provided. The present invention particularly provides a co-processed excipient composition and a method of producing the same. More particularly, it relates to a co-processed binary mixture of crosslinked polyvinylpyrrolidone and calcium silicate; wherein the weight ratio of crosslinked polyvinylpyrrolidone and calcium silicate is in the range of 1:1 to 20:1. The binary mixture when combined with a poorly soluble drug enhances its dissolution and extent of release.

Abstract: An image filter and method of smoothing pixel values. A pixel value of a pixel to be smoothed is compared with block average pixel values of each of a plurality of pixel blocks. The pixel to be smoothed may be downstream from each of the pixel blocks. If the difference between the pixel value and each of the block average pixel values is less than a corresponding sigma threshold value for each of the pixel blocks, a first sigma filter utilizing the block average pixel values is applied to the pixel to be smoothed. If the difference between the pixel value and any one of the block average pixel values is not less than a corresponding sigma threshold value, a second sigma filter is applied to the pixel to be smoothed.

Abstract: A packet processing engine is disclosed which comprises (a) packet processor for sniffing the packets and for analyzing traffic, and (b) core engine for packet processing. The core engine comprises means for extraction of protocols to build protocol analysis data and means for protocol-based analysis of the packets.