Abstract: A computer-implemented critical path method (CPM) scheduling system and method integrates carbon emissions associated with construction activities and permits a user to schedule a construction project including those activities. Information is stored regarding one or more milestones, phases, and activities associated with the project. The activity information includes interdependency and carbon emissions information associated with the activity. Based on the milestone information, phase information, and activity information, one or more of the following is calculated: a project schedule; identification, duration, date, and total carbon emission information for key activities; duration, date, and total carbon emission information for phases; and date and total carbon emission information for milestones.

Abstract: Disclosed are systems and methods that provide a novel framework for decision intelligence (DI)-based drug determinations. The disclosed framework can leverage a dynamically and recursively trained artificial intelligence/machine learning (AI/ML) ensemble configuration to analyze genomic data and functions that arrive from the same. Ensemble determinations and applications can increase the accuracy of the training, validation, and external testing sets associated with drug discovery and personalization. The ensemble-based computerized framework can be configured for analysis of samples using an ensemble algorithm trained with a binary mutation data and a hierarchical clustering data, which can enable determinations of drug efficacy and patent stratification.

Abstract: A memory built in self test (MBIST) controller of an MBIST circuit outputs first data. One or more errors is injected in the first data to produce second data. The second data is stored in the memory block. The memory block outputs the second data stored in the memory block. The MBIST controller receives the second data and detects an error in the second data based on a comparison with the first data, the error indicative of a failure of the MBIST. The MBIST controller provides an indication of failure of the MBIST to a processing core external to the MBIST circuit which performs diagnostic action in response to receiving the indication of failure of the MBIST. The processing core validates implementation of the diagnostic action.

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

Abstract: A memory built in self test (MBIST) controller of an MBIST circuit outputs first data. One or more errors is injected in the first data to produce second data. The second data is stored in the memory block. The memory block outputs the second data stored in the memory block. The MBIST controller receives the second data and detects an error in the second data based on a comparison with the first data, the error indicative of a failure of the MBIST. The MBIST controller provides an indication of failure of the MBIST to a processing core external to the MBIST circuit which performs diagnostic action in response to receiving the indication of failure of the MBIST. The processing core validates implementation of the diagnostic action.

Abstract: According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.

Abstract: In one embodiment, a TVS semiconductor device includes a P-N diode that is connected in parallel with a bipolar transistor wherein a breakdown voltage of the bipolar transistor is less than a breakdown voltage of the P-N diode.

Abstract: In a general aspect, a semiconductor device can include a heavily-doped substrate of a first conductivity type, a lightly-doped epitaxial layer of a second conductivity type disposed on the heavily-doped substrate, and a heavily-doped epitaxial layer of the second conductivity type disposed on the lightly-doped epitaxial layer. The heavily-doped epitaxial layer can have a doping concentration that is greater than a doping concentration of the lightly-doped epitaxial layer. At least a portion of the heavily-doped substrate can be included in a first terminal of a Zener diode, and at least a portion of the lightly-doped epitaxial layer and at least a portion of the heavily-doped epitaxial layer can be included in a second terminal of the Zener diode. The semiconductor device can further include a termination trench that extends through the heavily-doped epitaxial layer and the lightly-doped epitaxial layer, and terminates in the heavily-doped substrate.

Abstract: In one embodiment, a TVS semiconductor device includes a P-N diode that is connected in parallel with a bipolar transistor wherein a breakdown voltage of the bipolar transistor is less than a breakdown voltage of the P-N diode.

Abstract: In one embodiment, a TVS semiconductor device includes a P-N diode that is connected in parallel with a bipolar transistor wherein a breakdown voltage of the bipolar transistor is less than a breakdown voltage of the P-N diode.

Abstract: In one embodiment, a TVS semiconductor device includes a P-N diode that is connected in parallel with a bipolar transistor wherein a breakdown voltage of the bipolar transistor is less than a breakdown voltage of the P-N diode.

Abstract: An ultra-low capacitance ESD protection device with an ultra-fast response time and a low turn-on voltage, and a high holding current. The device may include: a heavily-doped p-type substrate; a lightly-doped n-type epitaxial layer with a heavily-doped n-type buried layer; and a semiconductor-controlled rectifier (SCR) structure within the epitaxial layer. The SCR structure includes, between a ground terminal and a pad terminal: a shallow P+ region within a moderately-doped n-type well to form an emitter-base junction of a trigger transistor; a shallow N+ region within a moderately-doped p-type well to form an emitter-base junction of a latching transistor, and a PN junction coupled to either of the shallow regions as a forward-biased series diode. To reduce capacitance, the n-type and p-type wells are separated by a lightly-doped portion of the epitaxial layer having a small lateral dimension for enhanced switching speed.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.

Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.

Abstract: A common mode filter coupled to a protection device. In accordance with an embodiment, the common mode filter has first and second coils, each coil having a spiral shape, a central region, an exterior region, a first terminal, and a second terminal, wherein the first terminal of the first coil is formed in a first portion of the central region, the first terminal of the second coil is formed in a second portion of the central region, and wherein the central region is laterally bounded by the first and second coils and the exterior region is not surrounded by the first and second coils. The protection device has a first terminal coupled to the first terminal of the first coil and a second terminal coupled to the first terminal of the second coil.

Abstract: A common mode filter coupled to a protection device. In accordance with an embodiment, the common mode filter has first and second coils, each coil having a spiral shape, a central region, an exterior region, a first terminal, and a second terminal, wherein the first terminal of the first coil is formed in a first portion of the central region, the first terminal of the second coil is formed in a second portion of the central region, and wherein the central region is laterally bounded by the first and second coils and the exterior region is not surrounded by the first and second coils. The protection device has a first terminal coupled to the first terminal of the first coil and a second terminal coupled to the first terminal of the second coil.

Abstract: In accordance with an embodiment, a semiconductor component, includes a common mode filter monolithically integrated with a protection device. The common mode filter includes a plurality of coils and the protection device has a terminal coupled to a first coil and another terminal coupled to a second coil.

Abstract: A common mode filter coupled to a protection device. In accordance with an embodiment, the common mode filter has first and second coils, each coil having a spiral shape, a central region, an exterior region, a first terminal, and a second terminal, wherein the first terminal of the first coil is formed in a first portion of the central region, the first terminal of the second coil is formed in a second portion of the central region, and wherein the central region is laterally bounded by the first and second coils and the exterior region is not surrounded by the first and second coils. The protection device has a first terminal coupled to the first terminal of the first coil and a second terminal coupled to the first terminal of the second coil.

Abstract: An ultra-low capacitance ESD protection device with an ultra-fast response time and a low turn-on voltage, and a high holding current. The device may include: a heavily-doped p-type substrate; a lightly-doped n-type epitaxial layer with a heavily-doped n-type buried layer; and a semiconductor-controlled rectifier (SCR) structure within the epitaxial layer. The SCR structure includes, between a ground terminal and a pad terminal: a shallow P+ region within a moderately-doped n-type well to form an emitter-base junction of a trigger transistor; a shallow N+ region within a moderately-doped p-type well to form an emitter-base junction of a latching transistor, and a PN junction coupled to either of the shallow regions as a forward-biased series diode. To reduce capacitance, the n-type and p-type wells are separated by a lightly-doped portion of the epitaxial layer having a small lateral dimension for enhanced switching speed.