Abstract: Embodiments of the present disclosure provide a power controller, a method of operating a power controller and a semiconductor memory system. In one embodiment, the power controller is for use with a memory and includes an access module configured to provide an active state of the memory to allow memory access. The power controller also includes a retain-till-access module configured to cycle a portion of the memory between the active state and a low leakage data retention state of the memory. The power controller further includes an expanded retain-till-access module configured to extend the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state.

Abstract: An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.

Abstract: An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.

Abstract: A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.

Abstract: Embodiments of the present disclosure provide a power controller, a method of operating a power controller and a semiconductor memory system. In one embodiment, the power controller is for use with a memory and includes an access module configured to provide an active state of the memory to allow memory access. The power controller also includes a retain-till-access module configured to cycle a portion of the memory between the active state and a low leakage data retention state of the memory. The power controller further includes an expanded retain-till-access module configured to extend the active state of the memory for a specified period of time before returning the memory to the low leakage data retention state.

Abstract: A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.

Abstract: A system for handling a power supply interruption in a non-volatile memory (10) is disclosed that includes a status indicator set (20) for each sector (16) of a non-volatile memory array (14). The status indicator set (20) is operable to indicate a status for the sector (16) and is independently erasable from the sector (16). A state machine (30) is operable to perform operations on the sectors (16). The state machine (30) is also operable to adjust the status indicator set (20) for a sector (16) prior to performing an operation on the sector (16) to indicate an interruption status and to adjust the status indicator set (20) for the sector (16) after completing the operation to indicate a completed status. Status indicator set (20) preferably includes alternatively employed active indicator sub-sets and erase indicator sub-sets.

Abstract: A flip-flop (14) is disclosed that includes an input circuit (50), a sense amplifier (52) and an output circuit (56). The input circuit (50) is operable to receive a data input signal and to generate complementary data signals. The sense amplifier (52) is coupled to the input circuit (50). The sense amplifier (52) is operable to receive the data signals from the input circuit (50) and to generate complementary amplified signals based on the data signals. The output circuit (56) is coupled to the sense amplifier (52). The output circuit (56) is operable to receive the amplified signals from the sense amplifier (52) and to generate complementary output signals based on the amplified signals.

Abstract: A flip-flop (14) is disclosed that includes an input circuit (50), a sense amplifier (52) and an output circuit (56). The input circuit (50) is operable to receive a data input signal and to generate complementary data signals. The sense amplifier (52) is coupled to the input circuit (50). The sense amplifier (52) is operable to receive the data signals from the input circuit (50) and to generate complementary amplified signals based on the data signals. The output circuit (56) is coupled to the sense amplifier (52). The output circuit (56) is operable to receive the amplified signals from the sense amplifier (52) and to generate complementary output signals based on the amplified signals.