Abstract: A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.

Abstract: In one aspect, a bump electrode of a semiconductor device is formed by providing a substrate including a pad electrode, forming a seed layer over the pad electrode, and forming a mask layer over the seed layer which includes an opening aligned over the pad electrode. A barrier plating layer is electroplated within the opening over the seed layer, and a bump plating layer is electroplated over the barrier plating layer. The mask layer is removed, and the seed layer is etched using the bump plating layer as a mask.

Abstract: The image sensor package includes: an image sensor chip including an image sensing unit which is positioned in an upper central portion thereof and including a plurality of chip bonding pads formed around the image sensing; a transparent board including a lower surface on which a first line electrically connected to the chip bonding pads is formed and the transparent board being arranged with the image sensor chip so that the lower surface faces the image sensing unit; and a plurality of second lines connected to the first line and extending along sidewalls of the image sensor chip to be exposed under a lower surface of the image sensor chip.

Abstract: A semiconductor package includes a semiconductor chip operatively attached to a conductive lead of a film circuit substrate by an indium-containing solder material and a silver-containing bump electrode, where the solder material is interposed between the conductive lead and the bump electrode.

Abstract: An image sensor package may include a transparent substrate, an image sensor chip having a sensing region disposed over the transparent substrate, a resin protection dam disposed between the image sensor chip and the transparent substrate inside a wiring pattern, the resin protection dam having an aperture formed to expose a sensing region of the image sensor chip and defining a cavity between the sensing region and the transparent substrate, a resin filled on the transparent substrate outside the resin protection dam, and a black matrix pattern disposed on each side of the transparent substrate and configured to block excess transmission of light.

Abstract: A semiconductor device comprises at the wafer level one or more ferrite structures adapted to dampen high frequency noise potentially apparent at signal lines and termination points within the semiconductor device. Related methods of forming said ferrite structures are also disclosed.

Abstract: A multi-path printed circuit board (PCB) comprising separate direct current (DC) and alternating current (AC) paths, and a power delivery system including the same are provided. The multi-path PCB comprises a plurality of planar layers, each comprising a metal layer, and a plurality of insulators interposed between the planar layers. The metal layers may have different conductivities. The power delivery system includes a power source, a semiconductor IC, and the multi-path PCB. The multi-path PCB is adapted to function as a power delivery path for delivering power from the power source to the semiconductor IC.

Abstract: In one embodiment, a film circuit substrate comprises an insulating film made of polyimide resin; a conductive circuit pattern formed on the insulating film, the circuit pattern including an inner lead to be connected with a conductive bump of a semiconductor chip through a bump bonding process; and a tin-indium alloy layer formed on the inner lead to produce an inter-metallic compound layer of AuxSn composition during the bump bonding process.