Abstract: A method and associated system for randomizing data to be stored in a memory storage device including, receiving a plurality of data bytes to be randomized at a memory controller and written to a page of a memory storage device, wherein the page comprises a plurality of data sectors and wherein each of the plurality of data sectors are configured to store a plurality of data bytes, randomizing a first portion of the plurality of data bytes using a first randomizer initialized by a first seed to generate a first portion of randomized data bytes and randomizing a second portion of the plurality of data bytes using a second randomizer initialized by a second seed to generate a second portion of randomized data bytes, wherein the first seed is uncorrelated with the second seed.

Abstract: A method and associated system for randomizing data to be stored in a memory storage device including, receiving a plurality of data bytes to be randomized at a memory controller and written to a page of a memory storage device, wherein the page comprises a plurality of data sectors and wherein each of the plurality of data sectors are configured to store a plurality of data bytes, randomizing a first portion of the plurality of data bytes using a first randomizer initialized by a first seed to generate a first portion of randomized data bytes and randomizing a second portion of the plurality of data bytes using a second randomizer initialized by a second seed to generate a second portion of randomized data bytes, wherein the first seed is uncorrelated with the second seed.

Abstract: Methods and apparatus are provided for controlling one or more memory devices connected to an input output (IO) circuit through a serial peripheral interface (SPI), to make any device which is in execute in place (XIP) mode exit XIP mode. An example method comprises driving an initial signal from the IO circuit onto the data pins for a first plurality of clock cycles, the initial signal causing any memory device not in XIP mode to treat subsequent signals as a dummy read, disabling a driving function of the IO circuit prior to a negative edge of a last one of the first plurality of clock cycles, stopping generation of clock signals for a transition waiting period after the first plurality of clock cycles, and activating a weak pull-up of the IO circuit to apply logic high on all of the data pins for a second plurality of clock cycles.