Abstract: A single queue for controlling a plurality of FIFO registers in a bus to bus interface. Assume that there are a number of FIFO's and that each FIFO has a number of packet sized locations. Then, the queue for controlling these FIFO's can be implemented from memory and pointers. The queue will have a number of slots, one for each packet location in a FIFO, each slot having one number of bits identifying the originating device and another number of bits identifying the set of pointers involved. The result is that a single queue will have a number of pointers to control a number of FIFO's. For a numerical example, assume two FIFO's connecting two data busses, eight devices connected to one bus, and a capacity of sixteen packets for each FIFO. In this case the queue will have sixteen slots and two sets of pointers. Each set has one pointer to identify the place at which data can be entered into the FIFO, and one pointer to identify the place at which data can be read from the FIFO.

Abstract: A bus interface for connecting two busses. It includes a first and second bus interface circuitry, central buffer and control circuitry. The control circuitry includes two control sequence circuitry for tracking and controlling the channels of data within a FIFO device. The sequence control circuitry includes a circular queue for providing a predetermined number of slots, each slot capable of containing the identity and the status of the channel of data already resident in the FIFO device, and capable of containing the identity of the channel of data pending residence in the FIFO device. The sequence control circuitry further includes two pointers for traversing the circular queue, slot by slot.

Abstract: The present invention is bus to bus interface for connecting a first bus to a second bus. A control means includes first and second control sequence means, substantially similar, for tracking and controlling the channels of data within a first and a second FIFO device. The first sequence control means includes first circular queue means for providing a predetermined number of slots, with each slot containing information regarding a channel of data already resident in first FIFO device, including the identity of the channel and the status of the channel, and containing information regarding a channel of data pending residence in first FIFO device, including the identity of the pending channel.

Abstract: A method is described for transferring data on a digital data bus system. The bus system includes a bus having a clock line for communicating a clock signal, address lines for communicating address signals, data lines for communicating data signals, and control lines for communicating control signals. A bus controller is connected to the bus. A plurality of devices are also connected to the bus. Each device has a predetermined address. The control lines include a bus grant line for communicating a bus grant signal that permits the devices addressed by the bus controller to send or receive data signals. According to the method, the bus controller generates a bus grant signal on the bus grant line and source address and destination address signals on the address lines. The devices receive the bus grant signal and the source address and destination address signals. The devices decode the source address and destination address signals in response to the bus grant signal.