Abstract: A technique for pinpointing and analyzing failures in complex integrated circuits is disclosed. A device-under-test (DUT) is powered up. Using Liquid Crystal (LC) or Photo-Emission (PE) techniques, leakage sites are identified. The leakage sites are associated with suspect circuit elements on the DUT, and candidate I/Os associated with the suspect failing elements are selected for subsequent testing. Using the candidate I/Os, a truncated set of test vectors is created, and applied to the DUT. While the DUT is running the truncated set of test vectors, the suspect elements are rigorously probed to identify failing elements. SEM images are preferably viewed simultaneously. In this manner, a log of failing elements is derived, for circuit or process re-design.