Abstract: A writeback cache coherency control module that can allow systems that do not support cache, or support only writethrough cache, to operate with a processor that has writeback cache. The control module also maintains coherency between main memory and cache in a writeback subsystem.

Abstract: The dual-ported micro-code sequencer includes a micro-code ROM which provides micro-code vectors to a latch for access by a data path logic unit. The latch allows for pipe-lining whereby one micro-code vector may be fetched while a second micro-code vector is being executed by the data path logic unit. Micro-code vectors provided by the ROM may include branched vectors controlled by branch conditions. Two output ports are provide to the micro-code ROM for simultaneously outputting both branch-taken vectors and branch-not-taken vectors to a multiplexer connected to the input of the latch. The multiplexer and the two output ports are provided such that both the branch-taken and the branch-not-taken vectors are available to the latch input. Thus, once the branch condition is evaluated the correct branched vector is latched for access by the data path logic. The dual-ported architecture substantially eliminates a problem in pipelined micro-code sequencers wherein a clock cycle is wasted if a branch is taken.

Abstract: A writeback cache coherency control module that can allow systems that do not support cache, or support only writethrough cache, to operate with a processor that has writeback cache. The control module also maintains coherency between main memory and cache in a writeback subsystem.

Abstract: The cache is turned on after every reset without the use of a software utility. For cold resets, the cache memory is kept off until the first software INT 19h is detected. During the INT 19h the cache is turned on. For a warm reset, the cache memory is turned on immediately after warm reset is detected.

Abstract: A method for supporting a writethrough cache in a computer system not otherwise supporting cache is disclosed. Cache coherency is guaranteed by a cache coherency module detecting the CPU programming a DMA controller to allow a device other than the CPU to transfer data to main memory and, until the data transfer is concluded, flushing the cache each time the CPU reads an address other than an address of a standard computer system component. The cache is also flushed upon conclusion of the data transfer. In computer systems including a bus master device, the cache is flushed whenever the cache coherency module detects the CPU reading an address other than an address of a standard computer system component and whenever the cache coherency module detects an interrupt other than a standard computer system interrupt. Also disclosed a method to automatically determine the range of cacheable addresses in the computer system and to turn on the cache after the computer system is reset.

Abstract: An apparatus and method for supporting a writethrough cache in a computer system not otherwise supporting cache is disclosed. Cache coherency is guaranteed by a cache coherency module detecting the CPU programming a DMA controller to allow a device other than the CPU to transfer data to main memory and, until the data transfer is concluded, flushing the cache each time the CPU reads an address other than an address of a standard computer system component. The cache is also flushed upon conclusion of the data transfer. In computer systems including a bus master device, the cache is flushed whenever the cache coherency module detects the CPU reading an address other than an address of a standard computer system component and whenever the cache coherency module detects an interrupt other than a standard computer system interrupt.