Abstract: A solid-state drive (SSD) may include a volatile buffer such as DRAM, a non-volatile memory (NVM) such as NAND Flash connected to the volatile buffer, and a capacitor connected to both, where the capacitor may have an energy capacity insufficient to supply the buffer and NVM using a normal supply voltage in a normal mode, but sufficient to supply the buffer and NVM using at least one reduced supply voltage in a temporary mode; and a related method may include programming data to the NVM by temporarily reducing the supply voltage to the NVM, and writing data to the NVM using the reduced supply voltage.

Abstract: A memory system includes a data channel, a controller configured to output a request across the data channel, and a memory device configured to store data and corresponding first parity, perform a decoding operation on the data to generate second parity in response to receipt of the request across the data channel, generate a difference from the first parity and the second parity, compress the difference, and enable the controller to access the data and the compressed difference to satisfy the request.

Abstract: A solid-state drive (SSD) may include a volatile buffer such as DRAM, a non-volatile memory (NVM) such as NAND Flash connected to the volatile buffer, and a capacitor connected to both, where the capacitor may have an energy capacity insufficient to supply the buffer and NVM using a normal supply voltage in a normal mode, but sufficient to supply the buffer and NVM using at least one reduced supply voltage in a temporary mode; and a related method may include programming data to the NVM by temporarily reducing the supply voltage to the NVM, and writing data to the NVM using the reduced supply voltage.

Abstract: A memory system includes a first plurality of nonvolatile memory devices of a first channel of the memory system, the first plurality of memory devices each being connected to a first communications bus; a second plurality of nonvolatile memory devices of a second channel of the memory system, the second plurality of memory devices each being connected to a second communications bus, and a first interconnection between a first memory device and a second memory device, the first memory device being a memory device from among the first plurality of nonvolatile memory devices, the second memory device being a memory device from among the second plurality of nonvolatile memory devices.

Abstract: A memory system includes a data channel, a controller configured to output a request across the data channel, and a memory device configured to store data and corresponding first parity, perform a decoding operation on the data to generate second parity in response to receipt of the request across the data channel, generate a difference from the first parity and the second parity, compress the difference, and enable the controller to access the data and the compressed difference to satisfy the request.

Abstract: A memory system includes a memory device, the memory device including a memory cell array and a compression encoder, the memory cell array including a first plurality of multi level cells (MLCs). The memory device is configured to generate a first partial page by performing one or more first sensing operations on the first plurality of MLCs using one or more first reference voltages, output the first partial page, generate a second partial page by performing a second sensing operation on the first plurality of MLCs based on a second reference voltage, the second reference voltage having a different voltage level than the one or more first reference voltages, generate a compressed second partial page by compressing the second partial page using the compression encoder, and output the compressed second partial page.

Abstract: A memory device includes a memory including memory cells, each of the memory cells being configured to store multiple bits of data. The memory device includes a controller configured to map the levels of the memory cells to bits such that a first half of the levels have a bit with a first binary value in a desired bit position and a second half of the levels have a bit with a second binary value in the desired bit position. The first half of the levels are a first group of consecutive levels, and the second half of the levels are a second group of consecutive levels. The controller is configured to generate a distribution for writing the data to the memory cells based on the mapping, and write the data to the memory cells based on the determined distribution.

Abstract: A method, executed by a memory controller, for estimating read levels of a nonvolatile memory includes reading voltages stored by memory cells of a page space within the nonvolatile memory to which pilot signals of a predetermined symbol are programmed. The number of memory cells are identified whose voltages, read from the page space, are less-than/greater-than a read-voltage applied in reading the voltages stored by the memory cells. A voltage to be applied for reading data stored in the page space is estimated based upon the identified number of memory cells.

Abstract: A method, executed by a memory controller, for estimating read levels of a nonvolatile memory includes reading voltages stored by memory cells of a page space within the nonvolatile memory to which pilot signals of a predetermined symbol are programmed. The number of memory cells are identified whose voltages, read from the page space, are less-than/greater-than a read-voltage applied in reading the voltages stored by the memory cells. A voltage to be applied for reading data stored in the page space is estimated based upon the identified number of memory cells.

Abstract: A method of operating a memory device is provided. The memory device includes a plurality of multi-level memory cells of which each memory cell includes L levels. Data which is expressed in a binary number is received. A P-length string is generated from the data. The P-length string is converted to a Q-length string. The Q-length string is distributed using I levels by eliminating at least one level from the L levels. P and Q represent binary bit lengths of the P-length string and the Q-length string. Q is greater than P. L represents a maximum number of levels which each multi-level memory cell has. I is smaller than L. The Q-length string is programmed into the plurality of memory cells.

Abstract: A method for reducing an amount of time needed for a single iteration of arithmetic encoding and arithmetic decoding is provided. Rescaling and range are calculated in parallel, range being a High parameter bound of a symbol-interval—a Low parameter bound of the symbol-interval+1. A new iHigh (iH) parameter and a new iLow (iL) parameter or a given/decoded symbol is found according to a cumulative frequency for an ith symbol. iH parameter and iL parameter rescaling is performed by shifting an amount of most significant bits of iH, iL in accordance with values of iH and iL. iRange is shifted to the left in accordance with a number of digits needed to represent iRange and a total number of bits reserved for iRange. A shifted iRange is divided by CF[N] and saved to Step_tmp while awaiting a result of H,L rescaling.

Abstract: A memory system includes a first plurality of nonvolatile memory devices of a first channel of the memory system, the first plurality of memory devices each being connected to a first communications bus; a second plurality of nonvolatile memory devices of a second channel of the memory system, the second plurality of memory devices each being connected to a second communications bus, and a first interconnection between a first memory device and a second memory device, the first memory device being a memory device from among the first plurality of nonvolatile memory devices, the second memory device being a memory device from among the second plurality of nonvolatile memory devices.

Abstract: A memory system includes a memory device, the memory device including, a memory cell array, and a compression encoder, the memory cell array including a first plurality of multi level cells (MLCs), the memory device being configured to, generate a first partial page by performing one or more first sensing operation on the first plurality of MLCs using one or more first reference voltages, output the first partial page, generate a second partial page by performing a second sensing operation on the first plurality of MLCs based on a second reference voltage, the second reference voltage having a different voltage level than the one or more first reference voltages, generate a second compressed partial page by compressing the second partial page using the compression encoder, and output the compressed second partial page.

Abstract: A memory device controller includes an error correction processor and a compression processor. The error correction processor is configured to obtain error location information for page data received from a source memory block over a memory channel. The compression processor is configured to compress the obtained error location information, and to output the compressed error location information to a target memory block without the page data over the same memory channel.

Abstract: At least one example embodiment discloses a memory storage device including a first memory and a controller configured to program a file into the first memory, read the file from the first memory upon receiving a request for the file from an external host, the request identifying requested manipulations to the file, and manipulate the file in accordance with the request.

Abstract: A method of operating a memory device is provided. The memory device includes a plurality of multi-level memory cells of which each memory cell includes L levels. Data which is expressed in a binary number is received. A P-length string is generated from the data. The P-length string is converted to a Q-length string. The Q-length string is distributed using I levels by eliminating at least one level from the L levels. P and Q represent binary bit lengths of the P-length string and the Q-length string. Q is greater than P. L represents a maximum number of levels which each multi-level memory cell has. I is smaller than L. The Q-length string is programmed into the plurality of memory cells.

Abstract: A memory controller includes a joint source-channel encoder circuit and a joint source-channel decoder circuit. The joint source-channel encoder circuit source encodes received data independent of whether the received data is compressible data, performs error correction coding on the source encoded data, and stores the source encoded data in a memory device. The joint source-channel decoder circuit performs source decoding of the data read from the memory device between iterations of error correction coding of the read data, and outputs the read data to at least one of a buffer memory and a storage device interface. The joint source-channel decoder circuit performs the source decoding of the read data independent of whether the read data is compressed data.

Abstract: A method for reducing an amount of time needed for a single iteration of arithmetic encoding and arithmetic decoding is provided. Resealing and range are calculated in parallel, range being a High parameter bound of a symbol-interval?a Low parameter bound of the symbol-interval+1. A new iHigh (iH) parameter and a new iLow (iL) parameter or a given/decoded symbol is found according to a cumulative frequency for an ith symbol. iH parameter and iL parameter resealing is performed by shifting an amount of most significant bits of iH, iL in accordance with values of iH and iL. iRange is shifted to the left in accordance with a number of digits needed to represent iRange and a total number of bits reserved for iRange. A shifted iRange is divided by CF[N] and saved to Step_tmp while awaiting a result of H,L resealing.

Abstract: A memory controller includes a joint source-channel encoder circuit and a joint source-channel decoder circuit. The joint source-channel encoder circuit source encodes received data independent of whether the received data is compressible data, performs error correction coding on the source encoded data, and stores the source encoded data in a memory device. The joint source-channel decoder circuit performs source decoding of the data read from the memory device between iterations of error correction coding of the read data, and outputs the read data to at least one of a buffer memory and a storage device interface. The joint source-channel decoder circuit performs the source decoding of the read data independent of whether the read data is compressed data.

Abstract: A low-density parity-check (LDPC) decoding method includes exchanging messages between check nodes and variable nodes based on scheduling information representing an order of exchanging messages between the check nodes and the variable nodes for an LDPC decoding, and performing the LDPC decoding based on the exchanged messages, wherein the scheduling information is determined by manipulating at least one of an order of the check nodes and an order of the variable nodes in an LDPC bipartite graph.