Abstract: Techniques are described for optimizing broadcast and collect primitives in switch fabrics. A switch is described for use in a switch fabric that includes a plurality of switches configured to interconnect a plurality of host devices. The switch includes a plurality of ports configured to receive and transmit data, and switch logic configured to facilitate transfer of the data among the ports. The switch logic is configured to implement a collect function in which responses from multiple destination host devices are collected and aggregated for transmission to a source host device. A first portion of the switch logic is configured to identify, count, and discard the responses in a data plane of the switch. A second portion of the switch logic is configured to generate an aggregated response in a control plane of the switch and introduce the aggregated response into the data plane for transmission toward the source host device.

Abstract: Global ports are supported in multi-switch systems having arbitrary topologies. In some implementations, global ports are implemented in a manner which makes the switch system robust in the face of link failure. In specific Ethernet implementations, global ports enable flooding, learning, forwarding, and link aggregation across the switch system.

Abstract: A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.

Abstract: Global ports are supported in multi-switch systems having arbitrary topologies. In some implementations, global ports are implemented in a manner which makes the switch system robust in the face of link failure. In specific Ethernet implementations, global ports enable flooding, learning, forwarding, and link aggregation across the switch system.

Abstract: Global ports are supported in multi-switch systems having arbitrary topologies. In some implementations, global ports are implemented in a manner which makes the switch system robust in the face of link failure. In specific Ethernet implementations, global ports enable flooding, learning, forwarding, and link aggregation across the switch system.

Abstract: A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.

Abstract: An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data using domino logic, and use the state-holding ability of the domino logic to implement pipelining without additional latches.

Abstract: A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.

Abstract: A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate.

Abstract: A shared memory is described having a plurality of receive ports and a plurality of transmit ports characterized by a first data rate. A memory includes a plurality of memory banks organized in rows and columns. Operation of the memory array is characterized by a second data rate. Non-blocking receive crossbar circuitry is operable to connect any of the receive ports with any of the memory banks. Non-blocking transmit crossbar circuitry is operable to connect any of the memory banks with any of the transmit ports. Buffering is operable to decouple operation of the receive and transmit ports at the first data rate from operation of the memory array at the second data rate. Scheduling circuitry is operable to control interaction of the ports, crossbar circuitry, and memory array to effect storage and retrieval of the data segments in the shared memory.

Abstract: An asynchronous circuit is described for processing units of data having a program order associated therewith. The circuit includes an N-way-issue resource comprising N parallel pipelines. Each pipeline is operable to transmit a subset of the units of data in a first-in-first-out manner. The asynchronous circuit is operable to sequentially control transmission of the units of data in the pipelines such that the program order is maintained.

Abstract: Global ports are supported in multi-switch systems having arbitrary topologies. In some implementations, global ports are implemented in a manner which makes the switch system robust in the face of link failure. In specific Ethernet implementations, global ports enable flooding, learning, forwarding, and link aggregation across the switch system.

Abstract: Techniques are described for optimizing broadcast and collect primitives in switch fabrics.

Abstract: A shared memory switch and switch fabric architecture are described which employ partitions of the shared memory to implement multiple, independent virtual congestion domains, thereby allowing congestion to be handled for different classes of traffic independently.

Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.

Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.

Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.

Abstract: Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.

Abstract: A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRAM state elements in a delay-insensitive manner.

Abstract: Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.