Patents by Inventor Uri Frank

Uri Frank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device, system and method of reduced-power memory address generation
    Patent number: 7634636
    Abstract: Devices, systems and methods of reduced-power memory address generation. For example, an apparatus includes: a carry save adder including at least a first set of adders and a second set of adders, wherein the adders of the first set are able to receive a first number of input bits and to produce a first number of outputs, and wherein adders of the second set are able to receive a second number of input bits and to produce the first number of outputs.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: December 15, 2009
    Assignee: Intel Corporation
    Inventors: Uri Frank, Ram Kenyagin
  • Apparatus and method for reduction of processor power consumption
    Patent number: 7363464
    Abstract: A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventors: Oded Liron, Uri Frank
  • Device, system and method of reduced-power memory address generation
    Publication number: 20070300039
    Abstract: Devices, systems and methods of reduced-power memory address generation. For example, an apparatus includes: a carry save adder including at least a first set of adders and a second set of adders, wherein the adders of the first set are able to receive a first number of input bits and to produce a first number of outputs, and wherein adders of the second set are able to receive a second number of input bits and to produce the first number of outputs.
    Type: Application
    Filed: June 22, 2006
    Publication date: December 27, 2007
    Inventors: Uri Frank, Ram Kenyagin
  • Apparatus and method for reduction of processor power consumption
    Publication number: 20050216697
    Abstract: A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.
    Type: Application
    Filed: January 31, 2005
    Publication date: September 29, 2005
    Inventors: Oded Liron, Uri Frank
  • Apparatus and method for reduction of power consumption in OS that use flat segmentation memory model
    Patent number: 6922769
    Abstract: A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: July 26, 2005
    Assignee: Intel Corporation
    Inventors: Oded Liron, Uri Frank
  • Apparatus and method for reduction of power consumption in OS that use flat segmentation memory model
    Publication number: 20040123066
    Abstract: A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Inventors: Oded Liron, Uri Frank