Abstract: In some examples, a method includes determining, during a boot sequence of a controller, a hash value for data of a block of a flash storage device, the block including executable code, determining a bit pattern based on a randomly generated number, extracting a subset of data bits of the hash value according to the bit pattern to obtain a snippet, and storing the snippet to a secure storage device.

Abstract: A method includes programming first and second values and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining that a first match exists corresponding to the first and second values, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to a determination that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming a fifth value into the first operand register and a sixth value into the second operand register and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit.

Abstract: A system for accelerating binary convolution operations of a neural network includes a set of destination registers, binary convolution circuitry, a decoder coupled to the binary convolution circuitry, and instruction fetch circuitry coupled to the decoder and configured to fetch a binary convolution instruction from an associated memory. The binary convolution instruction specifies input data, weight data, and the set of destination registers for performing a binary convolution operation. The decoder receives the binary convolution instruction from the instruction fetch circuitry and causes the input data and the weight data to be provided to the binary convolution circuitry. In response, the binary convolution circuitry performs the binary convolution operation on the input data and the weight data to produce output data and stores the output data in the set of destination registers.

Abstract: System and methods for using channel quality reports to reduce inter-band interference are disclosed. Channel information is received at a first wireless communication device from a second wireless communication device. The first wireless device is operating in a first frequency range, and the second wireless device is operating in a second frequency range. The first frequency range is adjacent to the second frequency range. A channel quality report is generated at the first wireless communication device. The channel quality report indicates that particular sub-bands in the first frequency range have low channel quality. The particular sub-bands are selected using the channel information.

Abstract: A method includes programming first and second values and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining that a first match exists corresponding to the first and second values, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to a determination that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming a fifth value into the first operand register and a sixth value into the second operand register and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit.

Abstract: An example apparatus includes: a memory; instructions in the apparatus; and a Bluetooth controller to execute the instructions to: enable circuitry to receive a synchronized transmission; determine if a synchronized transmission is received during a first duration; increment the first duration to a second duration as a result of not receiving the synchronized transmission during the first duration; and determine a third duration based on a determined difference in time between enabling circuitry to receive a synchronized transmission and receiving the synchronized transmission.

Abstract: An example apparatus includes: a memory; instructions in the apparatus; and a Bluetooth controller to execute the instructions to: enable circuitry to receive a synchronized transmission; determine if a synchronized transmission is received during a first duration; increment the first duration to a second duration as a result of not receiving the synchronized transmission during the first duration; and determine a third duration based on a determined difference in time between enabling circuitry to receive a synchronized transmission and receiving the synchronized transmission.

Abstract: In some examples, a method includes determining, during a boot sequence of a controller, a hash value for data of a block of a flash storage device, the block including executable code, determining a bit pattern based on a randomly generated number, extracting a subset of data bits of the hash value according to the bit pattern to obtain a snippet, and storing the snippet to a secure storage device.

Abstract: A Wi-Fi device in a WLAN network includes a processor and a transceiver adapted to be coupled to an antenna, and a power saving medium access in congested network environments algorithm that is activated after a Wi-Fi connection is established with its access point (AP). A Traffic Indication Map (TIM) bitmap in a TIM information element received in a beacon frame from the AP is analyzed to determine whether more than a predetermined number of bits (X) are set to indicate the AP has ?1 buffered frame for ones of the Wi-Fi devices to conclude whether the WLAN is in a congested environment. When in a congested environment, transmissions responsive to the beacon are postponed by entering a sleep mode for a random period of time (P). After P expires, the sleep mode is exited and a poll frame is transmitted to the AP to try to gain medium access.

Abstract: In some examples, a method includes determining, during a boot sequence of a controller, a hash value for data of a block of a flash storage device, the block including executable code, determining a bit pattern based on a randomly generated number, extracting a subset of data bits of the hash value according to the bit pattern to obtain a snippet, and storing the snippet to a secure storage device.

Abstract: A Wi-Fi device in a WLAN network includes a processor and a transceiver adapted to be coupled to an antenna, and a power saving medium access in congested network environments algorithm that is activated after a Wi-Fi connection is established with its access point (AP). A Traffic Indication Map (TIM) bitmap in a TIM information element received in a beacon frame from the AP is analyzed to determine whether more than a predetermined number of bits (X) are set to indicate the AP has ?1 buffered frame for ones of the Wi-Fi devices to conclude whether the WLAN is in a congested environment. When in a congested environment, transmissions responsive to the beacon are postponed by entering a sleep mode for a random period of time (P). After P expires, the sleep mode is exited and a poll frame is transmitted to the AP to try to gain medium access.

Abstract: An example apparatus includes: a memory; instructions in the apparatus; and a Bluetooth controller to execute the instructions to: enable circuitry to receive a synchronized transmission; determine if a synchronized transmission is received during a first duration; increment the first duration to a second duration as a result of not receiving the synchronized transmission during the first duration; and determine a third duration based on a determined difference in time between enabling circuitry to receive a synchronized transmission and receiving the synchronized transmission.

Abstract: A technique for controlling a processing device. The technique includes receiving, from a first register, input feature values. The technique also includes receiving, from a second register, weight values. The technique further includes receiving first addresses of output registers. The technique also includes performing a matrix multiplication of the input feature values and weight values in parallel to obtain matrix multiplication results. The technique further includes providing the matrix multiplication results to the output registers.

Abstract: A method includes programming first and second values and a first compare enable command into respective first operand, second operand, and first compare enable command registers in a hardware comparator circuit. The method includes determining that a first match exists corresponding to the first and second values, programming a third value into the first operand register and a fourth value into the second operand register, and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit. In response to a determination that a second match exists corresponding to the third and fourth values, the method includes asserting a success interrupt signal, programming a fifth value into the first operand register and a sixth value into the second operand register and programming a second compare enable command into a second compare enable command register in the hardware comparator circuit.

Abstract: An example apparatus includes: a memory; instructions in the apparatus; and a Bluetooth controller to execute the instructions to: enable circuitry to receive a synchronized transmission; determine if a synchronized transmission is received during a first duration; increment the first duration to a second duration as a result of not receiving the synchronized transmission during the first duration; and determine a third duration based on a determined difference in time between enabling circuitry to receive a synchronized transmission and receiving the synchronized transmission.

Abstract: An example apparatus includes: a memory; instructions in the apparatus; and a Bluetooth controller to execute the instructions to: enable circuitry to receive a synchronized transmission; determine if a synchronized transmission is received during a first duration; increment the first duration to a second duration as a result of not receiving the synchronized transmission during the first duration; and determine a third duration based on a determined difference in time between enabling circuitry to receive a synchronized transmission and receiving the synchronized transmission.

Abstract: A method includes receiving, by a device, a portion of a data packet from a peer device during a reception time period, decoding a portion of a protocol data unit (PDU) of the data packet, decoding at least a portion of a header of the PDU, determining that the data packet is an empty packet according to the header, and aborting, by the device, reception of a remaining portion of the data packet to early terminate the reception time period.

Abstract: In some examples, a method includes determining, during a boot sequence of a controller, a hash value for data of a block of a flash storage device, the block including executable code, determining a bit pattern based on a randomly generated number, extracting a subset of data bits of the hash value according to the bit pattern to obtain a snippet, and storing the snippet to a secure storage device.

Abstract: A hardware direct memory access controller including an input port configured to receive data from an electronic device for direct memory access transfer, an output port configured to provide data for direct memory access, and processing circuitry is disclosed. The processing circuitry is configured to receive data comprising a header and payload from the electronic device via the input port, parse the header to determine data parameters including a transaction length and an input data format, and select a target destination for the data based at least in part on the data parameters. The processing circuitry is also configured to allocate memory within the target destination based at least in part on the transaction length, and to format the payload for direct memory access based at least in part on the data parameters, and to transfer the formatted payload for storage within the allocated memory within the target destination via the output port using direct memory access.

Abstract: Systems and methods for Transmission Control Protocol (TCP) acknowledgement (ACK) packet suppression are described. In various implementations, these systems and methods may be applicable to low-power communications. For example, a method may include receive a transport packet at a transport layer; de-encapsulating the transport packet using a transport protocol to identify a security packet; communicating the security packet to a security layer by the transport layer; communicating an acknowledgement signal to the transport layer from the security layer in response to receiving the security packet; suppressing an acknowledgement packet at the transport layer in response to receiving the acknowledgement signal; adding an acknowledgment indication to a next data packet to be sent after the suppress action; and sending the next data packet.