Patents by Inventor Uri Weiser
Uri Weiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220075669Abstract: A method for non-blocking multithreading, the method may include (a) providing, during a deep neural network (DNN) calculation iteration, to a shared computational resource, input information units related to multiple DNN threads; (b) determining whether to reduce a numerical precision of one or more DNN calculations related to at least one of the multiple DNN threads, and (c) executing, based on the determining, DNN calculations on at least some of the input information units to provide one or more results of the DNN processing.Type: ApplicationFiled: September 8, 2021Publication date: March 10, 2022Applicant: Technion Research and Development Foundation Ltd.Inventors: Gil SHOMRON, Uri WEISER
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Patent number: 10878906Abstract: NAND-based content addressable memory is provided with a memory cell including two programmable resistive elements, such as memristors. These memory cells can be used to provide a programmable resistive address decoder. Such decoders can improve computer hardware performance in various ways: 1) improved translation lookaside buffers, 2) improved cache memory, and 3) by eliminating physical addresses entirely.Type: GrantFiled: February 13, 2018Date of Patent: December 29, 2020Assignee: TECHNION RESEARCH & DEVELOPMENT FOUNDATION LIMITEDInventors: Leonid Yavits, Ran Ginosar, Uri Weiser
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Publication number: 20200192675Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.Type: ApplicationFiled: November 29, 2019Publication date: June 18, 2020Inventors: Avinoam Kolodny, Uri Weiser, Shahar Kvatinsky
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Publication number: 20200192701Abstract: A multi-thread systolic array includes a plurality of processing elements, each including a processor. Each of the processing elements is configured to: receive a plurality of first inputs from a respective first input source; receive a plurality of second inputs from a respective second input source; the plurality of first inputs and the plurality of second inputs being arranged as a plurality of pairs corresponding to a plurality of threads; schedule, for each operation cycle of the processor, a certain thread of the plurality of threads; and execute a computation operation for the certain thread.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Inventors: Tal HOROWITZ, Uri WEISER, Zuguang WU, Huibin LUO, Yoni CHOUKROUN
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Publication number: 20200051634Abstract: NAND-based content addressable memory is provided with a memory cell including two programmable resistive elements, such as memristors. These memory cells can be used to provide a programmable resistive address decoder. Such decoders can improve computer hardware performance in various ways: 1) improved translation lookaside buffers, 2) improved cache memory, and 3) by eliminating physical addresses entirely.Type: ApplicationFiled: February 13, 2018Publication date: February 13, 2020Inventors: Leonid YAVITS, Ran GINOSAR, Uri WEISER
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Patent number: 10521237Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.Type: GrantFiled: March 19, 2014Date of Patent: December 31, 2019Assignee: TECHNION RESEARCH AND DEVELOPMENT FOUNDATION LTDInventors: Avinoam Kolodny, Uri Weiser, Shahar Kvatinsky
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Patent number: 10417005Abstract: A data processing apparatus is provided comprising a front-end interface electronically coupled to a main processor. The front-end interface is configured to receive data stored in a repository, in particular an external storage and/or a network, determine whether the data is a single-access data or a multiple-access data by analyzing an access parameter designating the data, route the multiple-access data for processing by the main processor, and route the single-access data for pre-processing by the front-end interface and routing results of the pre-processing to the main processor.Type: GrantFiled: September 11, 2017Date of Patent: September 17, 2019Assignee: Huawei Technologies Co., Ltd.Inventors: Uri Weiser, Tal Horowitz, Jintang Wang
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Publication number: 20170371676Abstract: A data processing apparatus is provided comprising a front-end interface electronically coupled to a main processor. The front-end interface is configured to receive data stored in a repository, in particular an external storage and/or a network, determine whether the data is a single-access data or a multiple-access data by analyzing an access parameter designating the data, route the multiple-access data for processing by the main processor, and route the single-access data for pre-processing by the front-end interface and routing results of the pre-processing to the main processor.Type: ApplicationFiled: September 11, 2017Publication date: December 28, 2017Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Uri WEISER, Tal HOROWITZ, Jintang WANG
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Publication number: 20140325192Abstract: A method and a device that includes a set of multiple pipeline stages, wherein the set of multiple pipeline stages is arranged to execute a first thread of instructions; multiple memristor based registers that are arranged to store a state of another thread of instructions that differs from the first thread of instructions; and a control circuit that is arranged to control a thread switch between the first thread of instructions and the other thread of instructions by controlling a storage of a state of the first thread of instructions at the multiple memristor based registers and by controlling a provision of the state of the other thread of instructions by the set of multiple pipeline stages; wherein the set of multiple pipeline stages is arranged to execute the other thread of instructions upon a reception of the state of the other thread of instructions.Type: ApplicationFiled: March 19, 2014Publication date: October 30, 2014Applicant: Technion Research and Development Foundation LTD.Inventors: Avinoam Kolodny, Uri Weiser, Shahar Kvatinsky
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Publication number: 20070124736Abstract: Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating system. When the operating system scheduler has no work to schedule on the idle thread units, the operating system may issue a halt or monitor/mwait or other instruction to place the thread unit into an idle state. While the thread unit is idle, from the operating system perspective, the thread unit may be utilized to perform speculative acceleration threads in order to accelerate threads running on non- idle thread units. The context of the idle thread unit is saved prior to execution of the acceleration thread and is restored when the operating system requires use of the thread unit. The acceleration threads are transparent to the operating system. Other embodiments are also described and claimed.Type: ApplicationFiled: November 28, 2005Publication date: May 31, 2007Inventors: Ron Gabor, Gad Sheaffer, Avi Mendelson, Uri Weiser, Hong Wang
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Patent number: 5450605Abstract: The specification discloses a method and apparatus for determining the length of variable-length instructions that appear sequentially in an instruction stream without differentiation. The apparatus may be used to facilitate parallel processing of such variable-length instructions by a computer system.Type: GrantFiled: January 28, 1993Date of Patent: September 12, 1995Assignee: Intel CorporationInventors: Edward Grochowski, Kenneth Shoemaker, Uri Weiser, Doron Orenstein
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Patent number: 5381533Abstract: An improved cache and organization particularly suitable for superscalar architectures. The cache is organized around trace segments of running programs rather than an organization based on memory addresses. A single access to the cache memory may cross virtual address line boundaries. Branch prediction is integrally incorporated into the cache array permitting the crossing of branch boundaries with a single access.Type: GrantFiled: March 30, 1994Date of Patent: January 10, 1995Assignee: Intel CorporationInventors: Alexander Peleg, Uri Weiser