Abstract: A package substrate for a semiconductor device includes a substrate core and a coupled inductor embedded in the substrate core. The coupled inductor may include a double clad laminate having a dielectric layer and first and second metal layers sandwiching the dielectric layer. The first and second metal layers may be patterned to define spiral windings. The coupled inductor may further include first and second magnetic core layers sandwiching the double clad laminate. Alternatively, the coupled inductor may include a magnetic core embedded in a dielectric substrate and first and second conductive windings surrounding the magnetic core. Each of the first and second conductive windings may include one or more first segments defined by metal patterning in a plane parallel to the magnetic core and one or more second segments defined by one or more conductive vias extending through the magnetic core or through dielectric surrounding the magnetic core.

Abstract: A package substrate for a semiconductor device includes a substrate core and a coupled inductor embedded in the substrate core. The coupled inductor may include a double clad laminate having a dielectric layer and first and second metal layers sandwiching the dielectric layer. The first and second metal layers may be patterned to define spiral windings. The coupled inductor may further include first and second magnetic core layers sandwiching the double clad laminate. Alternatively, the coupled inductor may include a magnetic core embedded in a dielectric substrate and first and second conductive windings surrounding the magnetic core. Each of the first and second conductive windings may include one or more first segments defined by metal patterning in a plane parallel to the magnetic core and one or more second segments defined by one or more conductive vias extending through the magnetic core or through dielectric surrounding the magnetic core.

Abstract: A package substrate for a semiconductor device includes a substrate core and a coupled inductor embedded in the substrate core. The coupled inductor may include a double clad laminate having a dielectric layer and first and second metal layers sandwiching the dielectric layer. The first and second metal layers may be patterned to define spiral windings. The coupled inductor may further include first and second magnetic core layers sandwiching the double clad laminate. Alternatively, the coupled inductor may include a magnetic core embedded in a dielectric substrate and first and second conductive windings surrounding the magnetic core. Each of the first and second conductive windings may include one or more first segments defined by metal patterning in a plane parallel to the magnetic core and one or more second segments defined by one or more conductive vias extending through the magnetic core or through dielectric surrounding the magnetic core.

Abstract: Multi-terminal capacitor devices and methods of making multi-terminal capacitor devices are described herein. The multi-terminal capacitor devices may include a plurality of individual capacitors arranged in a single device layer, such as high surface area capacitors. A individual capacitor may include an aluminum foil-based electrode, an aluminum oxide dielectric layer conformal with the aluminum foil-based electrode, and a conductive material electrode, such as a conducting polymer or a conductive ceramic, in conformal contact with the dielectric layer.

Abstract: A package substrate for a semiconductor device includes a first substrate core and an inductor embedded in the first substrate core, the inductor including a magnetic core embedded in the first substrate core and a conductive winding surrounding the magnetic core, the conductive winding including one or more first segments defined by metal patterning on the first substrate core and one or more second segments defined by one or more conductive vias extending through the first substrate core. The package substrate may further include a capacitor embedded in the first substrate core and/or in a second substrate core vertically stacked with the first substrate core.

Abstract: A package substrate for a semiconductor device includes a first substrate core and an inductor embedded in the first substrate core, the inductor including a magnetic core embedded in the first substrate core and a conductive winding surrounding the magnetic core, the conductive winding including one or more first segments defined by metal patterning on the first substrate core and one or more second segments defined by one or more conductive vias extending through the first substrate core. The package substrate may further include a capacitor embedded in the first substrate core and/or in a second substrate core vertically stacked with the first substrate core.

Abstract: Multi-terminal capacitor devices and methods of making multi-terminal capacitor devices are described herein. The multi-terminal capacitor devices may include a plurality of individual capacitors arranged in a single device layer, such as high surface area capacitors. A individual capacitor may include an aluminum foil-based electrode, an aluminum oxide dielectric layer conformal with the aluminum foil-based electrode, and a conductive material electrode, such as a conducting polymer or a conductive ceramic, in conformal contact with the dielectric layer.

Abstract: An intergrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

Abstract: Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.

Abstract: An integrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

Abstract: Some features pertain to an integrated device that includes a dielectric layer configured as a base for the integrated device, several redistribution metal layers in the dielectric layer, a first wafer level die coupled to a first surface of the dielectric layer, and a second wafer level die coupled to the first wafer level die. The dielectric layer includes several dielectric layers. In some implementations, the first wafer level die is coupled to the redistribution metal layers through a first set of interconnects. In some implementations, the first wafer level die includes several through substrate vias (TSVs). In some implementations, the second wafer level die is coupled to the redistribution metal layers through a first set of interconnects, the TSVs, a second set of interconnects, and a set of solder balls. In some implementations, the integrated device includes an encapsulation layer that encapsulates the first and second wafer level dies.

Abstract: An integrated interposer between a first component and a second component includes a substrate. The substrate may have thermal and/or mechanical properties with values lying between the thermal and/or mechanical properties of the first component and the second component. Active devices are disposed on a first surface of the substrate. A contact layer is coupled to the active devices and configured to couple at least the first component and a third component to the integrated interposer. At least one through via(s) is coupled to the contact layer and extends through the substrate to a second surface of the substrate. An interconnect layer is disposed on the second surface of the substrate and coupled to the at least one through via(s). The interconnect layer is configured to couple the second component to the integrated interposer.

Abstract: An integrated circuit package includes a core such as a thin glass core with through-core vias. A photo-patternable material is disposed directly on surfaces of the core and in the through-core vias and is selectively patterned to expose at least an exposed portion of the surface of the core and the through-core vias. A metal layer, such as copper, is disposed in the exposed portion of the core and in the through-core vias. A mechanical handler frame may be used to clamp together the various layers including the core and the photo-patternable material. The photo-patternable material that remains after patterning is permanent, and prevents the mechanical handler frame from directly contacting the core. Thus the photo-patternable material provides mechanical support to the core and protects the core from the mechanical handler.

Abstract: Systems and methods include a first semiconductor die with a substrate having a first side and a second side opposite to the first side. A first set of electronic elements is integrated on the first side. A second set of electronic elements is integrated on the second side. One or more through-substrate vias through the substrate are used to couple one or more of the first set of electronic elements and one or more of the second set of electronic elements. The through-substrate vias may be through-silicon vias (TSVs) or a through-glass vias (TGVs). The first semiconductor die may be stacked with a second semiconductor die, with the first side or the second side of the first semiconductor die interfacing an active side of the second semiconductor die.

Abstract: In a particular embodiment, an apparatus includes a stress sensor located on a first side of a semiconductor device. The apparatus further includes circuitry located on a second side of the semiconductor device. The stress sensor is configured to detect stress at the semiconductor device. In another particular embodiment, a method includes receiving data from a stress sensor located on a first side of a packaged semiconductor device. The packaged semiconductor device includes circuitry located on a second side of the packaged semiconductor device. The data indicates stress detected by the stress sensor. The method further includes performing a test associated with the packaged semiconductor device based on the data.

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, a first metal redistribution layer coupled to one of the metal layers, and a second metal redistribution layer coupled to the first metal redistribution layer. The first and second metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the integrated device also includes a third metal redistribution layer. The third metal redistribution layer is coupled to the first and second metal redistribution layers. The third metal redistribution layer is a via. In some implementations, the first, second, and third metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the first, second, and third redistribution layers form a set of windings for the toroid inductor.

Abstract: An integrated interposer between a first component and a second component includes a substrate. The substrate may have thermal and/or mechanical properties with values lying between the thermal and/or mechanical properties of the first component and the second component. Active devices are disposed on a first surface of the substrate. A contact layer is coupled to the active devices and configured to couple at least the first component and a third component to the integrated interposer. At least one through via(s) is coupled to the contact layer and extends through the substrate to a second surface of the substrate. An interconnect layer is disposed on the second surface of the substrate and coupled to the at least one through via(s). The interconnect layer is configured to couple the second component to the integrated interposer.

Abstract: Some features pertain to an integrated device that includes a dielectric layer configured as a base for the integrated device, several redistribution metal layers in the dielectric layer, a first wafer level die coupled to a first surface of the dielectric layer, and a second wafer level die coupled to the first wafer level die. The dielectric layer includes several dielectric layers. In some implementations, the first wafer level die is coupled to the redistribution metal layers through a first set of interconnects. In some implementations, the first wafer level die includes several through substrate vias (TSVs). In some implementations, the second wafer level die is coupled to the redistribution metal layers through a first set of interconnects, the TSVs, a second set of interconnects, and a set of solder balls. In some implementations, the integrated device includes an encapsulation layer that encapsulates the first and second wafer level dies.

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, a first metal redistribution layer coupled to one of the metal layers, and a second metal redistribution layer coupled to the first metal redistribution layer. The first and second metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the integrated device also includes a third metal redistribution layer. The third metal redistribution layer is coupled to the first and second metal redistribution layers. The third metal redistribution layer is a via. In some implementations, the first, second, and third metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the first, second, and third redistribution layers form a set of windings for the toroid inductor.

Abstract: An integrated circuit package is disclosed that includes a first-pitch die and a second-pitch die. The second-pitch die interconnects to the second-pitch substrate through second-pitch substrates. The first-pitch die interconnects through first-pitch interconnects to an interposer adapter. The pitch of the first-pitch interconnects is too fine for the second-pitch substrate. But the interposer adapter interconnects through second-pitch interconnects to the second-pitch substrate and includes through substrate vias so that I/O signaling between the first-pitch die and the second-pitch die can be conducted through the second-pitch substrate and through the through substrate vias in the interposer adapter.