Patents by Inventor Usame Ceylan

Usame Ceylan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10600142
    Abstract: A compute unit accesses a chunk of bits that represent indices of vertices of a graphics primitive. The compute unit sets values of a first bit to indicate whether the chunk is monotonic or ordinary, second bits to define an offset that is determined based on values of indices in the chunk, and sets of third bits that determine values of the indices in the chunk based on the offset defined by the second bits. The compute unit writes a compressed chunk represented by the first bit, the second bits, and the sets of third bits to a memory. The compressed chunk is decompressed and the decompressed indices are written to an index buffer. In some embodiments, the indices are decompressed based on metadata that includes offsets that are determined based on values of the indices and bitfields that indicate characteristics of the indices.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 24, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Usame Ceylan, Young In Yeo, Todd Martin, Vineet Goel
  • Patent number: 10417791
    Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 17, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Usame Ceylan, Vineet Goel, Juraj Obert, Liang Li
  • Publication number: 20190172173
    Abstract: A compute unit accesses a chunk of bits that represent indices of vertices of a graphics primitive. The compute unit sets values of a first bit to indicate whether the chunk is monotonic or ordinary, second bits to define an offset that is determined based on values of indices in the chunk, and sets of third bits that determine values of the indices in the chunk based on the offset defined by the second bits. The compute unit writes a compressed chunk represented by the first bit, the second bits, and the sets of third bits to a memory. The compressed chunk is decompressed and the decompressed indices are written to an index buffer. In some embodiments, the indices are decompressed based on metadata that includes offsets that are determined based on values of the indices and bitfields that indicate characteristics of the indices.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 6, 2019
    Inventors: Usame Ceylan, Young In Yeo, Todd Martin, Vineet Goel
  • Publication number: 20180293761
    Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.
    Type: Application
    Filed: June 12, 2018
    Publication date: October 11, 2018
    Inventors: Usame Ceylan, Vineet Goel, Juraj Obert, Liang Li
  • Patent number: 9779534
    Abstract: In an example, rendering graphics data includes determining, with a graphics processing unit (GPU), a texture offset for a current segment of a plurality of ordered segments of a dashed line, where the texture offset for the current segment of the plurality of ordered segments is based on an accumulation of lengths of segments that precede the current segment in the order, and pixel shading the current segment including applying the texture offset to determine a location of the current segment.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: October 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Vineet Goel, Usame Ceylan
  • Publication number: 20170243375
    Abstract: Techniques are described for using a texture unit to perform operations of a shader processor. Some operations of a shader processor are repeatedly executed until a condition is satisfied, and in each execution iteration, the shader processor accesses the texture unit. Techniques are described for the texture unit to perform such operations until the condition is satisfied.
    Type: Application
    Filed: February 18, 2016
    Publication date: August 24, 2017
    Inventors: Usame Ceylan, Vineet Goel, Juraj Obert, Liang Li
  • Patent number: 9619853
    Abstract: This disclosure is directed to techniques for performing GPU-accelerated path rendering. A GPU is described that is configured to receive data indicative of a path segment of a path to be rendered, tessellate the path segment into a plurality of primitives, and render at least one of a fill area and a stroke area for the path segment based on the plurality of primitives. The techniques of this disclosure may be used to improve the performance of path rendering operations, to reduce memory bandwidth requirements needed to perform path rendering operations, and/or to reduce the memory footprint needed to perform path rendering operations.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: April 11, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Vineet Goel, Usame Ceylan
  • Patent number: 9483862
    Abstract: A graphics processing unit (GPU) comprises a memory, and at least one processor configured to: receive a primitive type buffer comprising a plurality of primitive type entries, wherein each of a plurality of vertices of a vertex buffer of the GPU are associated with one or more of the plurality of primitive type entries, determine primitives based on the plurality of vertices and the associated one or more primitive type entries, and rendering, by the GPU, the primitives based on the plurality of vertices and the associated one or more primitive type entries of the primitive type buffer.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 1, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Vineet Goel, Usame Ceylan
  • Patent number: 9330495
    Abstract: The present disclosure provides for path rendering including receiving, with a graphics processing unit (GPU), data indicative of a path segment of a path to be rendered. The systems and methods render the path segment by performing a fill of the path segment, which includes tessellating the path segment into a first plurality of primitives including a triangle per primitive, storing a first plurality of primitives in a stencil buffer, and drawing a bounding box of the path segment and rendering the bounding box with a stencil test enabled. The systems and methods also stroke the path segment, including tessellating the path into a second plurality of primitives, re-tessellating the second plurality of primitives, cutting the second plurality of primitives according to a dash pattern, creating a cap at a location of a cut, and creating a triangulation of a stroke and rasterizing the stroke based on the triangulation.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 3, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Vineet Goel, Usame Ceylan
  • Patent number: 9305397
    Abstract: Systems and methods for a tessellation are described. These systems and methods may divide the domain into a plurality of portions, including a first portion. The systems and methods may also determine coordinates for vertices for a first set of shapes that reside within the first portion, wherein each shape of the first set of shapes includes at least one vertex on a first edge of the first portion. After determining coordinates for the vertices for the first set of shapes, the systems and methods may determine coordinates for vertices for a second set of shapes that reside within the first portion. Each shape of the second set of shapes shares at least one vertex with at least one shape of the first set of shapes and none of the shapes of the second set of shapes includes a vertex on the first edge of the first portion.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: April 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Usame Ceylan, Vineet Goel
  • Patent number: 9299181
    Abstract: In an example rendering graphics data includes determining a stencil parameter that indicates a sampling rate for determining a coverage value for each antialiased pixel of a path of an image, determining, separately from the stencil parameter, a render target parameter that indicates a memory allocation for each antialiased pixel of the path, and rendering the path using the stencil parameter and the render target parameter.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: March 29, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Vineet Goel, Usame Ceylan
  • Patent number: 9275498
    Abstract: A tessellation unit of a graphics processing unit (GPU) determines domain coordinates for vertices of a received primitive. The tessellation unit outputs the determined domain coordinates for the vertices. The tessellation unit further determines that a domain type for the received primitive is not one of tri, isoline, or quad domain, and outputs information indicative of a graphical feature associated with one or more of the determined domain coordinates when the domain type is not one of the tri, isoline, or quad domain.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 1, 2016
    Assignee: Qualcomm Incorporated
    Inventors: Usame Ceylan, Vineet Goel
  • Patent number: 9123168
    Abstract: Systems and methods for a tessellation are described. For tessellation, a tessellation unit may divide a domain into a plurality of portions, where at least one portion is a contiguous portion. The tessellation unit may output domain coordinates of primitives along diagonal strips within the contiguous portion to increase the likelihood that patch coordinates that correspond to the domain coordinates are stored in a reuse buffer.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: September 1, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chunhui Mei, Nariman Moezzi Madani, Vineet Goel, Usame Ceylan, Guofang Jiao
  • Patent number: 9076260
    Abstract: Techniques described in the disclosure are generally related to determining the manner in which to connect points that reside along an outer ring edge and an inner ring edge for purposes of tessellation. For example, a two-dimensional (2D) stitching table may define the manner in which points along the edges should be connected together to form a plurality of primitives. The techniques may index the 2D stitching table to retrieve entry values that define the manner in which the points along the edges should be connected together.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: July 7, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Vineet Goel, Usame Ceylan
  • Publication number: 20150178974
    Abstract: A graphics processing unit (GPU) comprises a memory, and at least one processor configured to: receive a primitive type buffer comprising a plurality of primitive type entries, wherein each of a plurality of vertices of a vertex buffer of the GPU are associated with one or more of the plurality of primitive type entries, determine primitives based on the plurality of vertices and the associated one or more primitive type entries, and rendering, by the GPU, the primitives based on the plurality of vertices and the associated one or more primitive type entries of the primitive type buffer.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Vineet Goel, Usame Ceylan
  • Publication number: 20150062124
    Abstract: In an example rendering graphics data includes determining a stencil parameter that indicates a sampling rate for determining a coverage value for each antialiased pixel of a path of an image, determining, separately from the stencil parameter, a render target parameter that indicates a memory allocation for each antialiased pixel of the path, and rendering the path using the stencil parameter and the render target parameter.
    Type: Application
    Filed: July 1, 2014
    Publication date: March 5, 2015
    Inventors: Vineet Goel, Usame Ceylan
  • Publication number: 20150062142
    Abstract: In an example, rendering graphics data includes determining, with a graphics processing unit (GPU), a texture offset for a current segment of a plurality of ordered segments of a dashed line, where the texture offset for the current segment of the plurality of ordered segments is based on an accumulation of lengths of segments that precede the current segment in the order, and pixel shading the current segment including applying the texture offset to determine a location of the current segment.
    Type: Application
    Filed: July 1, 2014
    Publication date: March 5, 2015
    Inventors: Vineet Goel, Usame Ceylan
  • Publication number: 20140210819
    Abstract: Systems and methods for a tessellation are described. For tessellation, a tessellation unit may divide a domain into a plurality of portions, where at least one portion is a contiguous portion. The tessellation unit may output domain coordinates of primitives along diagonal strips within the contiguous portion to increase the likelihood that patch coordinates that correspond to the domain coordinates are stored in a reuse buffer.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 31, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Chunhui Mei, Nariman Moezzi Madani, Vineet Goel, Usame Ceylan, Guofang Jiao
  • Publication number: 20140111513
    Abstract: Systems and methods for a tessellation are described. These systems and methods may divide the domain into a plurality of portions, including a first portion. The systems and methods may also determine coordinates for vertices for a first set of shapes that reside within the first portion, wherein each shape of the first set of shapes includes at least one vertex on a first edge of the first portion. After determining coordinates for the vertices for the first set of shapes, the systems and methods may determine coordinates for vertices for a second set of shapes that reside within the first portion. Each shape of the second set of shapes shares at least one vertex with at least one shape of the first set of shapes and none of the shapes of the second set of shapes includes a vertex on the first edge of the first portion.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 24, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Usame Ceylan, Vineet Goel
  • Publication number: 20140063013
    Abstract: Techniques described in the disclosure are generally related to determining the manner in which to connect points that reside along an outer ring edge and an inner ring edge for purposes of tessellation. For example, a two-dimensional (2D) stitching table may define the manner in which points along the edges should be connected together to form a plurality of primitives. The techniques may index the 2D stitching table to retrieve entry values that define the manner in which the points along the edges should be connected together.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Vineet Goel, Usame Ceylan