Patents by Inventor Ushasri Merugu

Ushasri Merugu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10816598
    Abstract: A system for debugging circuits includes an integrated circuit configured to implement a circuit under test and a logic analyzer controller coupled to the circuit under test. The system includes a host computing system configured to communicate with the logic analyzer controller and provide a debug command to the logic analyzer controller. The logic analyzer controller, in response to the debug command, controls operation of the circuit under test.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: October 27, 2020
    Assignee: Xilinx, Inc.
    Inventors: Ushasri Merugu, Mahesh Sankroj, Sharat Babu Kotamraju
  • Patent number: 10067189
    Abstract: Disclosed circuitry includes input-output pads, receive flip-flops, and transmit flip-flops coupled to the input-output pads. Data path control circuitry is coupled to data path control flip-flops, the receive flip-flops and the transmit flip-flops. The data path control circuitry is configured to selectably couple the receive flip-flops and the transmit flip-flops to the input-output pads in response to states of the data path control flip-flops. Clock control circuitry is coupled to clock control flip-flops, the receive flip-flops and the transmit flip-flops. The clock control circuitry is configured to selectably apply one of multiple clock signals to the receive flip-flops and the transmit flip-flops in response to states of the clock control flip-flops. A first scan chain is coupled to the clock control flip-flops and the data path control flip-flops. A second scan chain is coupled to the receive flip-flops and the transmit flip-flops.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 4, 2018
    Assignee: XILINX, INC.
    Inventors: Banadappa V. Shivaray, Ahmad R. Ansari, Sanjeeva R. Duggampudi, Pramod Surathkal, Ushasri Merugu, Bommana S. Rao, Sowmya Sheela Thati, Shashidhar S. Krishnamurthy
  • Patent number: 10062454
    Abstract: Disclosed approaches for probing signals in a plurality of clock domains include inputting unsynchronized trigger signals from the plurality of clock domains to a plurality of instances of a multi-synchronizer circuit, respectively. Each instance of the multi-synchronizer circuit includes a plurality of synchronizer circuits. One or more of the plurality of synchronizer circuits synchronizes the respective unsynchronized trigger signal with one clock signal from the plurality of clock domains. Output of one of the one or more synchronizer circuits in each instance of the multi-synchronizer circuit is selected as a respective synchronized trigger signal. A trigger equation is evaluated based on a state of each respective synchronized trigger signal. A final trigger signal is generated based the evaluating of the trigger equation, a trigger marker is stored in a memory in response to a state of the final trigger signal, and states of probed signals are stored in the memory.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: August 28, 2018
    Assignee: XILINX, INC.
    Inventors: Ushasri Merugu, Mahesh Sankroj, Sudheer K. Koppolu, Siva V. N. Hemasunder Tallury
  • Patent number: 8983790
    Abstract: Systems and methods gather data for debugging a circuit-under-test. The system includes a trigger-and-capture circuit, a data compressor, a direct memory access controller, and a memory controller. The trigger-and-capture circuit is coupled to the circuit-under-test for receiving signals from the circuit-under-test. The trigger-and-capture circuit is configured to assert a trigger signal when the signals match a trigger condition. The data compressor is configured to loss-lessly compress the signals into compressed data. The direct memory access controller is configured to generate write and read requests. The write requests write the compressed data to a memory integrated circuit die, and the read requests read the compressed data from the memory integrated circuit die. The memory controller is configured to perform the write and read requests.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: March 17, 2015
    Assignee: Xilinx, Inc.
    Inventors: Ushasri Merugu, Siva V. N. Hemasunder Tallury, Sudheer Kumar Koppolu