Abstract: The invention relates to a method for address translation in a system running multiple levels of virtual machines containing a hierarchically organized translation lookaside buffer comprising at least two linked hierarchical sub-units, a first sub-unit comprising a lookaside buffer for some higher level address translation levels, and the second sub-unit comprising a lookaside buffer for some lower level address translation levels, and said second sub-unit being arranged to store TLB index address information of the upper level sub-unit as tag information in its lower level TLB structure, comprising the steps of collecting intermediate address translation results on different virtual machine levels; and buffering the intermediate translation results in the translation lookaside buffer.

Abstract: Processing within a computing environment is facilitated by filtering requests of the computing environment. A processing unit that receives a request determines whether it is to perform the request. This determination is made by, for instance, comparing an identifier of the request with an identifier of the processing unit making the determination. If there is a mismatch, then the request is blocked. Other processing within the computing environment is also facilitated by selectively using buffer entries. The selection criteria is based, for instance, on identifier information.

Abstract: A program product, a translation lookaside buffer and a related method for operating the TLB is provided.

Abstract: Buffered indexing for a computer's array such as a cache is used to synchronize parent entries with children and allow background invalidation (that is, suspending the invalidation should a new request of the array come in, resuming the invalidation after the request is satisfied) of the child entries. A method for synchronization uses linking of (multiple) entries in lower-level tables to single entries in a higher-level table with a buffered index value. This index value increments each time the higher-level entry is replaced or invalidated (and thus disassociated with its corresponding lower-level entries). Multiple sets of index values are maintained, so that when one set is exhausted, processing can continue with one of the other sets. All corresponding lower-level entries with index values from the old (dirty) set can then be scrubbed (invalidated) while new entries are built from the new (clean) set.

Abstract: Buffered indexing for a computer's array such as a cache is used to synchronize parent entries with children and allow background invalidation (that is, suspending the invalidation should a new request of the array come in, resuming the invalidation after the request is satisfied) of the child entries. A method for synchronization uses linking of (multiple) entries in lower-level tables to single entries in a higher-level table with a buffered index value. This index value increments each time the higher-level entry is replaced or invalidated (and thus disassociated with its corresponding lower-level entries). Multiple sets of index values are maintained, so that when one set is exhausted, processing can continue with one of the other sets. All corresponding lower-level entries with index values from the old (dirty) set can then be scrubbed (invalidated) while new entries are built from the new (clean) set.

Abstract: Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that address translation is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of page indices, which indicates whether the address translation can continue. If address translation can continue, the restriction is ignored. The processing unit includes a processor or a pageable entity, as examples.

Abstract: Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that fetching of storage keys is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of addresses, which indicates whether the fetching can continue. If fetching can continue, the restriction is ignored.

Abstract: The present invention relates to a central processing unit comprising: (a) a number of functional units (A, B, . . . , N), (b) at least one module for processing of a function call received from one of the functional units, the module having a decoder to obtain an instruction address from the function call, a memory for storing a plurality of control instructions and for storing a plurality of branch instructions, each control instruction having an assigned instruction address for a next instruction and each branch instruction having assigned at least two alternative instruction addresses for a next instruction, first logic circuitry for processing of the branch instructions in order to select one of the at least two alternative instruction addresses of one of the branch instructions, second logic circuitry for processing of the control instructions in order to return a result in response to the function call.

Abstract: Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that address translation is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of page indices, which indicates whether the address translation can continue. If address translation can continue, the restriction is ignored. The processing unit includes a processor or a pageable entity, as examples.

Abstract: Processing within a computing environment is facilitated by filtering requests of the computing environment. A processing unit that receives a request determines whether it is to perform the request. This determination is made by, for instance, comparing an identifier of the request with an identifier of the processing unit making the determination. If there is a mismatch, then the request is blocked. Other processing within the computing environment is also facilitated by selectively using buffer entries. The selection criteria is based, for instance, on identifier information.

Abstract: Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that fetching of storage keys is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of addresses, which indicates whether the fetching can continue. If fetching can continue, the restriction is ignored.

Abstract: The present invention generally relates to shared-memory multiprocessor systems, such as IBM ESA/390 or RS/6000 systems, and deals more particularly with a method and system for sharing a second-level translation lookaside buffer (TLB 2) between several CPUs (30a, . . . 30d) for improving the performance and reducing the chip area required to buffer the results of virtual-to-absolute address translations. The inventive TLB2 organization comprises several small arrays (32a, . . . 32d) dedicated to particular CPUs, providing an interface to a major array (21), which is shared between the CPUs. The dedicated arrays 32a, . . . 32d) are required to fulfill the architected constraints and link several CPUs to the commonly used shared array (21).

Abstract: The present invention generally relates to shared-memory multiprocessor systems, such as IBM ESA/390 or RS/6000 systems, and deals more particularly with a method and system for sharing a second-level translation lookaside buffer (TLB 2) between several CPUs (30a, . . . 30d) for improving the performance and reducing the chip area required to buffer the results of virtual-to-absolute address translations. The inventive TLB2 organization comprises several small arrays (32a, . . . 32d) dedicated to particular CPUs, providing an interface to a major array (21), which is shared between the CPUs. The dedicated arrays 32a, . . . 32d) are required to fulfill the architected constraints and link several CPUs to the commonly used shared array (21).

Abstract: The basic idea comprised of the present invention is to provide a translation lookaside buffer (TLB) arrangement which advantageously uses two buffers, a small first level TLB1 and a larger second level TLB2. The second level TLB feeds address information to the first level TLB when the desired virtual address is not contained in the first level TLB. According to the invention the second level TLB is structured advantageously comprising two n-way set-associative sub-units of which one, a higher level unit covers some higher level address translation levels and the other one, a lower level unit, covers some lower level translation level. According to the present invention, some address information holds some number of middle level virtual address (MLVA) bits, i.e., 8 bits, for example, being able to serve as an index address covering the address range of the higher level sub-unit.

Abstract: A method and system for renaming registers of said system is proposed in which mixed instruction sets, e.g. 32 bit and 64 bit instructions are carried out concurrently in one program. In case of an instruction sequence of a preceding 64 bit instruction and one or more 32 bit instructions to be executed in-order after the 64 bit instruction and where the 32 bit instructions having a data dependence to the preceding 64 bit instruction, said rest of the register range changed by the preceding 64 bit instruction is copied to the corresponding location in a target register of the succeeding 32 bit instruction, at least if the same logical register is specified by the 32 bit instruction as it was specified by the preceding 64 bit instruction. The copy source is addressed by the register number and hold in a list (28).

Abstract: A system and method for register renaming and allocation in an out-of-order processing system which allows the use of a minimum number of physical registers is described. A link list allows concatenation of a physical register representing a certain instance of the corresponding logical register to the physical register representing the next instance of the same logical register. By adding and removing links in this link list, it is possible to manage the assignment of physical registers to logical registers dynamically. Both the physical registers representing speculative instances and the physical registers representing in-order instances are administrated together. This is done by means of an in-order list, which indicates the physical registers that actually represent the architected state of the machine.

Abstract: The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers.Therefore, there have to exist several physical rename registers per logical register. The oldest one of said rename registers defines the architected state of the computer system, the in-order state.The invention provides a method for administration of the various register instances. Both the registers representing the in-order state and the various rename instances are kept in one common circular buffer. There exist two pointers per logical register: The first one, the in-order pointer, points to the register that represents the in-order state, the second one, the rename pointer, points to the most recent rename instance.

Abstract: A shifting structure and method which separates a shifting operation into partial shifts which may be executed in different pipeline staged is described herein. In a first pipe stage, an operand is read out and at least one partial shift is accomplished by placing the operand or parts thereof into registers coupled to a shift unit. The shift unit, in a second pipe stage, finalizes the shifting operation executing the remaining partial shifts, thereby reducing the time required for the total shifting operation. A control string is derived in the shift unit based on the shift amount to correct the output of the shifted result as well as providing for parity prediction therefor.

Abstract: A process is disclosed to serialize instructions that are to be processed serially in a multiprocessor system, with the use of a token, where the token can be assigned on request to one of the processors, which thereupon has the right to execute the command. If the command consists of dristibuted tasks, the token remains blocked until the last dependent task belonging to the command has also been executed. It is only then that the token can be assigned to another instruction. Moreover, a device is described to manage this token, which features three states: a first state, in which the token is available, a second state, in which the token is assigned to one of the processors, and a third state, in which the token is blocked, because dependent tasks still have to be carried out. Moreover, a circuit is disclosed with which the token principle that is introduced can be implemented in a simple manner.