Patents by Inventor Ute Rothammer

Ute Rothammer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Layered semiconductor substrate with reduced bow having a group III nitride layer and method for manufacturing it
    Patent number: 10192739
    Abstract: A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from ?50 ?m to 50 ?m.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: January 29, 2019
    Assignee: SILTRONIC AG
    Inventors: Peter Storck, Guenter Sachs, Ute Rothammer, Sarad Bahadur Thapa, Helmut Schwenk, Peter Dreier, Frank Muemmler, Rudolf Mayrhuber
  • LAYERED SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING IT
    Publication number: 20140048848
    Abstract: A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from ?50 ?m to 50 ?m.
    Type: Application
    Filed: May 23, 2012
    Publication date: February 20, 2014
    Applicant: SILTRONIC AG
    Inventors: Peter Storck, Guenter Sachs, Ute Rothammer, Sarad Bahadur Thapa, Helmut Schwenk, Peter Dreier, Frank Muemmler, Rudolf Mayrhuber