Patents by Inventor Uthayarajan A/L Rasalingam

Uthayarajan A/L Rasalingam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948924
    Abstract: A combined semiconductor device package includes a first semiconductor device package having a first semiconductor chip housed within a first enclosure, and a first substrate coupled to the first enclosure. The first substrate includes first solder balls and second solder balls, each in electrical communication with the first semiconductor chip. The first semiconductor device further includes conductive pads directly coupled to the first substrate. The conductive pads are in electrical communication with the first and second solder balls. The combined semiconductor device package further includes a second semiconductor device package having a second semiconductor chip housed within a second enclosure, and third solder balls in electrical communication with the second semiconductor chip, and coupled to the conductive pads of the first semiconductor device package.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: April 2, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Uthayarajan A L Rasalingam, Toh Kok Wei
  • Patent number: 11832383
    Abstract: Multi-signal vias for use with differential pair signals in electronic devices. The electronic devices include a printed circuit board having a first side and a second side opposite the first side, a first conductive trace on the first side of the substrate and a second conductive trace on the first side of the substrate. The printed circuit board also includes a shared via, which includes a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are separated by a non-conductive portion. The first conducive trace is coupled to the first conductive portion of the shared via and the second conductive trace is coupled to the second conductive portion of the shared via.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: November 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Uthayarajan A/L Rasalingam, Hock Boon Khaw
  • Publication number: 20230369791
    Abstract: A connector for communicatively coupling an electronic device to a host device is provided. The connector includes a mating side and a termination side for surface mounting the connector to the electronic device. The mating side includes a first contact and a second contact. The termination side includes a printed circuit board and a grid of connection points provided on a bottom surface of the printed circuit board. The first contact is communicatively coupled to a first connection point in the grid of connection points and the second contact is communicatively coupled to a second connection point in the grid of connection points.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Inventor: Uthayarajan A/L Rasalingam
  • Publication number: 20230371209
    Abstract: A thermal dissipation device for use with electronic assemblies or devices and that includes a heat conductive plate configured to thermally couple to one or more packaged components on a first side of the heat conductive plate. The thermal dissipation device further includes a heat conductive post coupled to a second side of the heat conductive plate. The heat conductive post includes a fin member rotatably coupled to the heat conductive post, which is configured to rotate about an axis of the heat conductive post to maximize both a flow of air across the fin member and thermal dissipation of heat from the heat conductive plate into the atmosphere.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Inventors: Uthayarajan A/L Rasalingam, Vijay A/L Mohanarao
  • Publication number: 20230371179
    Abstract: A lead finger has a v-shaped contact point and a u-shaped profile. The u-shaped profile includes a portion that is disposed below a top surface of a PCB. The v-shaped contact point aids in guiding a host connector clip to an ideal location of the lead finger, where the ideal location may allow for more contact surface area and better contact to the host connector clip. The u-shaped profile may reduce impact force of the host connector clip to the lead finger.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Inventors: Uthayarajan A/L RASALINGAM, Muhammad Afif Bin Abu HUSSEIN
  • Publication number: 20230343690
    Abstract: A semiconductor device package includes a substrate having a top and bottom surface and an electrical circuit. There is a semiconductor die electrically connected to the electrical circuit of the substrate. There are N adjacent first electrical contacts and N is an integer greater than 1. The N adjacent first electrical contacts are positioned within a first contact area on the bottom surface of the substrate. There is a second electrical contact that is associated with N independent common signals that are electrically connected at a single second electrical contact. The second electrical contact is positioned within a second contact area on the bottom surface of the substrate that is smaller than the first contact area. The second electrical contact reduces the total area required on the substrate for common signal contacts to allow for additional non-common signal contacts to be included in the semiconductor device package.
    Type: Application
    Filed: April 20, 2022
    Publication date: October 26, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Uthayarajan A/L Rasalingam, Roel Gabriel Hernando Taburnal
  • Patent number: 11778748
    Abstract: A data storage device including a first printed circuit board (PCB) and a second PCB. The first PCB includes a controller, an interface configured to interface with a host device, and a first connector. The second PCB includes a non-volatile memory and a second connector. The second connector is configured to couple to the first connector to establish a communication connection between the controller and the non-volatile memory.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: October 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Uthayarajan A/L Rasalingam, Go Beng Siong
  • Publication number: 20230268290
    Abstract: A semiconductor package includes a substrate having a first surface, and a second surface opposite the first surface. The substrate includes a connection region having a first array of contact pads, and a peripheral region surrounding the connection region and having additional contact pads. A semiconductor die having an array of electrical contacts and thermal contacts, is connected to the first array of contact pads and to the additional contact pads. A plate is coupled to a top surface of the semiconductor die and there is at least one pin projecting from the plate toward the first substrate. The pin is disposed within a channel that extends between the plate and the additional contact. The plate, channel and pin improve the heat dissipation capabilities of the semiconductor device package.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Uthayarajan A/L Rasalingam, Janice Jia Min Ling
  • Publication number: 20230156921
    Abstract: A data storage device includes a substrate and one or more grid array integrated circuit packages. The grid array integrated circuit package includes at least one self-alignment pin having a tapered shape. The substrate includes one or more connection pads to receive the grid array integrated circuit packages. The connection pads include at least one self-alignment receptacle that receives the self-alignment pins such that the grid array integrated circuit packages maintain an alignment with an associated connection pad of the substrate.
    Type: Application
    Filed: November 16, 2021
    Publication date: May 18, 2023
    Inventors: Uthayarajan A/L Rasalingam, Alexander Beh
  • Publication number: 20220392877
    Abstract: A combined semiconductor device package includes a first semiconductor device package having a first semiconductor chip housed within a first enclosure, and a first substrate coupled to the first enclosure. The first substrate includes first solder balls and second solder balls, each in electrical communication with the first semiconductor chip. The first semiconductor device further includes conductive pads directly coupled to the first substrate. The conductive pads are in electrical communication with the first and second solder balls. The combined semiconductor device package further includes a second semiconductor device package having a second semiconductor chip housed within a second enclosure, and third solder balls in electrical communication with the second semiconductor chip, and coupled to the conductive pads of the first semiconductor device package.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 8, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Uthayarajan A/L Rasalingam, Toh Kok Wei
  • Publication number: 20220271456
    Abstract: A data storage device including a first printed circuit board (PCB) and a second PCB. The first PCB includes a controller, an interface configured to interface with a host device, and a first connector. The second PCB includes a non-volatile memory and a second connector. The second connector is configured to couple to the first connector to establish a communication connection between the controller and the non-volatile memory.
    Type: Application
    Filed: February 19, 2021
    Publication date: August 25, 2022
    Inventors: Uthayarajan A/L Rasalingam, Go Beng Siong