Patents by Inventor Utkarsh GARG

Utkarsh GARG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250181597
    Abstract: A data processing system includes: a processor; a memory containing programming instructions for execution by the processor; and a network interface for communicating with an Artificial Intelligence (AI) engine. The programming instructions include an application for generating written content, the application having a function to generate and submit a structured query regarding the written content to the AI engine to generate feedback on an assessed quality of the written content, the structured query structured to prompt for feedback in a variety of specified categories for the written content. The application further includes a user interface to display the feedback on the written content and provide an option to a user to implement the feedback to revise the written content.
    Type: Application
    Filed: December 27, 2024
    Publication date: June 5, 2025
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Aleksey Aleksandrovich SOKOLOV, Utkarsh GARG, Siqing CHEN, Warren Anthony ALDRED, Saket KUMAR, Cheng YANG, Bhavuk JAIN, Mahaveer Bhavarlal KOTHARI, Alyssa Rachel MAYO, Tashfeen AHMED, Zhang LI, Olivier Michel Nicolas GAUTHIER, Christine Lauren MAYER, Jesse Alexander FREITAS
  • Patent number: 12216674
    Abstract: A data processing system includes: a processor; a memory containing programming instructions for execution by the processor; and a network interface for communicating with an Artificial Intelligence (AI) engine. The programming instructions include an application for generating written content, the application having a function to generate and submit a structured query regarding the written content to the AI engine to generate feedback on an assessed quality of the written content, the structured query structured to prompt for feedback in a variety of specified categories for the written content. The application further includes a user interface to display the feedback on the written content and provide an option to a user to implement the feedback to revise the written content.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: February 4, 2025
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Aleksey Aleksandrovich Sokolov, Utkarsh Garg, Siqing Chen, Warren Anthony Aldred, Saket Kumar, Cheng Yang, Bhavuk Jain, Mahaveer Bhavarlal Kothari, Alyssa Rachel Mayo, Tashfeen Ahmed, Zhang Li, Olivier Michel Nicolas Gauthier, Christine Lauren Mayer, Jesse Alexander Freitas
  • Publication number: 20240303247
    Abstract: A data processing system includes: a processor; a memory containing programming instructions for execution by the processor; and a network interface for communicating with an Artificial Intelligence (AI) engine. The programming instructions include an application for generating written content, the application having a function to generate and submit a structured query regarding the written content to the AI engine to generate feedback on an assessed quality of the written content, the structured query structured to prompt for feedback in a variety of specified categories for the written content. The application further includes a user interface to display the feedback on the written content and provide an option to a user to implement the feedback to revise the written content.
    Type: Application
    Filed: March 6, 2023
    Publication date: September 12, 2024
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Aleksey Aleksandrovich SOKOLOV, Utkarsh GARG, Siqing CHEN, Warren Anthony ALDRED, Saket KUMAR, Cheng YANG, Bhavuk JAIN, Mahaveer Bhavarlal KOTHARI, Alyssa Rachel MAYO, Tashfeen AHMED, Zhang LI, Olivier Michel Nicolas GAUTHIER, Christine Lauren MAYER, Jesse Alexander FREITAS
  • Publication number: 20230418556
    Abstract: Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder circuit. The integrated circuit includes a carry generation circuit configured to receive a first input and a second input to generate a carry, and a carry propagation circuit configured to receive the first input, the second input, and a third input to generate a propagated output. The integrated circuit further includes a carry output generation circuit configured to receive the generated carry and the propagated output to generate a final carry as an output, and a sum generation circuit configured to generate a sum output. The sum generation circuit includes the carry generation circuit and is configured to receive the first input, the second input, and generated carry to generate an exclusive NOR output, and further uses the generated exclusive NOR output and the third input to generate the sum output.
    Type: Application
    Filed: August 23, 2022
    Publication date: December 28, 2023
    Inventors: Debojyoti Banerjee, Abhishek Ghosh, Raghavendra Ramakant Shirodkar, Rakesh Dimri, Utkarsh Garg
  • Publication number: 20200266185
    Abstract: Example embodiments provide a four input multiplexer integrated circuit (MXT4) associated with an integrated circuit (IC) and a method for reducing area and power of an integrated circuit (IC) using a MXT4, the MXT4 including a complementary signal generator circuit configured to receive first and second selection signals and to generate first and second complementary selection signals based on respective ones of the first and the second selection signals; and a p-type metal oxide semiconductor (PMOS) and an n-type metal oxide semiconductor (NMOS) stack switch circuit configured to transmit at least one input signal to an output based on the first and the second selection signals and the first and the second complementary selection signals.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sajal MITTAL, Abhishek GHOSH, Utkarsh GARG
  • Patent number: 10672756
    Abstract: Example embodiments provides a full adder integrated circuit (ADDF) for improving area and power of an integrated circuit (IC). The method includes receiving three input signals and generating three corresponding complementary output signals. Further, the method includes generating an internal signal using two complementary output signals out of the generated three corresponding complementary output signals, and one of the three input signals. Further, the method includes generating an output summation signal using a complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and a complementary internal signal of the generated internal signal. Further, the method includes generating a carry-out signal using two complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and the complementary internal signal.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: June 2, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sajal Mittal, Abhishek Ghosh, Utkarsh Garg
  • Publication number: 20200144245
    Abstract: Example embodiments provides a full adder integrated circuit (ADDF) for improving area and power of an integrated circuit (IC). The method includes receiving three input signals and generating three corresponding complementary output signals. Further, the method includes generating an internal signal using two complementary output signals out of the generated three corresponding complementary output signals, and one of the three input signals. Further, the method includes generating an output summation signal using a complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and a complementary internal signal of the generated internal signal. Further, the method includes generating a carry-out signal using two complementary output signal out of the generated three corresponding complementary output signals, the generated internal signal and the complementary internal signal.
    Type: Application
    Filed: January 2, 2019
    Publication date: May 7, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sajal MITTAL, Abhishek GHOSH, Utkarsh GARG