Abstract: A computational system with a primary processor and a secondary processor executing executable code, the secondary processor executing at least one clock cycle behind the primary processor. The primary processor comprising (i) two primary delay buffers, including a final primary delay buffer, and (ii) a primary historical storage buffers operably linked to the final primary delay buffer. The secondary processor including a secondary delay buffer and a secondary historical storage buffer operably liked with the secondary delay buffer. The system including a circuit for performing a comparison between first data values from the final primary delay buffer and second data values from the secondary delay buffer. The system configured, if the first data values and the second data values do not match, for storing the first data values in the primary historical storage buffer and the second data values in the secondary historical storage buffer.