Patents by Inventor Utpal Bhattacharyya

Utpal Bhattacharyya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11714948
    Abstract: The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include receiving, using a processor, one or more DFM rules files from at least one PCB fabricator and importing the one or more DFM rules files to a DFM rule aggregator database. Embodiments may also include grouping one or more rules associated with the one or more DFM rules files using an automated or manual operation. Embodiments may further include performing automatic or manual rule aggregation on the grouped rules based upon, at least in part, rules aggregation information including a DFM template file.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: August 1, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Utpal Bhattacharyya, Randall Scott Lawson, Edward Brian Acheson, Amit Sharma
  • Patent number: 10691868
    Abstract: The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include an electronic computer aided design (“CAD”) system configured to receive one or more design rules and to receive one or more manufacturing rules. The CAD system may be further configured to analyze design database objects from the electronic design with respect to the manufacturing rules. The CAD system may generate a manufacturing output file, based upon, at least in part, the analyzing. Embodiments may also include a signoff computer aided manufacturing (“CAM”) station configured to receive the manufacturing output file. The CAM station may be configured to attempt to validate the manufacturing output file.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 23, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Randall Scott Lawson, Utpal Bhattacharyya, Edward B. Acheson, Robert Roesler
  • Patent number: 9449130
    Abstract: Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: September 20, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taranjit Singh Kukal, Steven Durrill, Utpal Bhattacharyya, Amit Sharma
  • Patent number: 9286421
    Abstract: Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: March 15, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taranjit Singh Kukal, Steven Durrill, Utpal Bhattacharyya, Amit Sharma