Abstract: This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device. The present invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices.

Abstract: This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices. Processing methods of the present invention are capable of making micro- and nano-scale electronic structures, such as T-gates, gamma gates, and shifted T-gates, having a selected non-uniform cross-sectional geometry. The present invention provides lithographic processing strategies for sub-pixel patterning in a single layer of photoresist useful for making and integrating device components comprising dielectric, conducting, metal or semiconductor structures having non-uniform cross-sectional geometries. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication platforms, and can be effectively integrated into existing photolithographic, etching and thin film deposition patterning strategies, systems and infrastructure.

Abstract: This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro-and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device. The present invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices.

Abstract: This invention provides processing steps, methods and materials strategies for making patterns of structures for electronic, optical and optoelectronic devices. Processing methods of the present invention are capable of making micro- and nano-scale electronic structures, such as T-gates, gamma gates, and shifted T-gates, having a selected non-uniform cross-sectional geometry. The present invention provides lithographic processing strategies for sub-pixel patterning in a single layer of photoresist useful for making and integrating device components comprising dielectric, conducting, metal or semiconductor structures having non-uniform cross-sectional geometries. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication platforms, and can be effectively integrated into existing photolithographic, etching and thin film deposition patterning strategies, systems and infrastructure.

Abstract: A method for providing a current state assessment of a life cycle management and support structure of an information technology environment which includes defining building block services wherein a building block service is any discrete benefit explicitly provided by a vendor to a customer of the vendor and the building block service has at least one of a physical product, a service and a solution, and describing the current state of the information technology environment with the building block services as a current state assessment is disclosed.