Abstract: Dual amplifying circuits having a magnetic tunnel junction device and a field effect transistor configured in a complementing set are disclosed herein. In one embodiment, the field effect transistor is operable to control a current level of a current operating signal flowing through the magnetic tunnel junction device. In another embodiment, the magnetic tunnel junction device is operable to control a voltage level of a voltage signal being applied to a gate terminal of the field effect transistor. The gain-bandwidth product of both embodiments is greater than the individual gain-bandwidth products of the individual devices through the elimination of noise contributing resistive type circuit elements.

Abstract: A system for measuring magnetic fields produced by an integrated circuit device-under-test includes a clock generator configured to generate a clock signal, a delay circuit configured to generate a delayed clock signal having a known delay relative to the clock signal, a pulse generator configured to generate a series of pulses having a frequency corresponding to a frequency of the clock signal, the pulses of the series of pulses being offset from the clock signal by the known delay, and a sensor having a property that varies in response to a magnetic field at the sensor. A sampling circuit connected to the sensor and to the pulse generator is configured to measure the property of the sensor at times corresponding to pulses of the series of pulses, and to produce a sampling signal having, for each pulse, a first value (e.g., a logical one) when the property of the sensor indicates that the magnetic field at the sensor exceeds a threshold amount and a second value (e.g.

Abstract: A hybrid superconducting-semiconducting field effect transistor-like circuit element comprised of a superconducting field effect transistor and a closely associated cryogenic semiconductor inverter for providing signal gain is described. The hybrid circuit functions nearly as an ideal pass gate in cryogenic cross-bar applications.

Abstract: Apparatus for converting superconductor low level signals to semiconductor signal levels utilizing a continuous superconductor to semiconductor converter circuit biased for maximum gain and without the need for a clocked reset signal. Employing a unique biasing arrangement utilizing two capacitors and one transistor, this circuit has long term bias voltage retention and good power supply noise rejection ratio.

Abstract: Superconducting-semiconducting hybrid memories are disclosed. These superconducting-semiconducting hybrid memories utilize semiconductor circuits to store information, and either superconducting or semiconducting or combinations of superconducting and semiconducting circuits, with at least some superconducting circuitry used, to write and read information. The state of memory cells in the hybrid memories is determined by utilizing superconductor current sensing schemes to detect currents in the bit-line, thereby avoiding any bit-line charging delays and other problems associated with purely semiconductor memories. Additional features of the superconducting-semiconducting hybrid memories include wide margins, dense packing of memory cells, low power dissipation and fast access times. Interface curcuitry for converting superconducting signals to signals compatible with semiconductor circuits and for converting semiconductor signals to signals compatible with superconducting circuits is also disclosed.

Abstract: A coaxial bump for connecting a die to a substrate includes a center post and a ground ring surrounding and shielding the center post. The center post may be a center conductor line, and the ground ring may be generally torus-shaped, nearly closed or completely closed. The coaxial bump provides very low crosstalk in chip-to-substrate interconnections and provides a constant impedance with negligible inductive discontinuity.

Abstract: A hybrid superconducting-semiconducting field effect transistor-like circuit element comprised of a superconducting field effect transistor and a closely associated cryogenic semiconductor inverter for providing signal gain is described. The hybrid circuit functions as a nearly ideal pass gate in cryogenic applications.

Abstract: A low-voltage CMOS interconnection circuit utilizing high-Tc superconducting tunnel junctions and interconnects for a very high speed interchip communication at low temperatures (4-77K). An improved driver produces very small current transients and has good immunity to noise from input voltage fluctuations, cross talk and simultaneous switching of drivers. An improved receiver includes a common gate CMOS receiver having a biasing stage and at least one amplifier stage and has the advantage of a large amplification and is self biasing.

Abstract: A bootstrapped CMOS driver circuit capable of driving large capacitance loads with small internal delays. Higher driving capability is achieved by using only n-channel transistors at the output and overdriving the transistors during the transitions. A total internal delay of less than one nanosecond for a driver may be provided with 100 ohms compatible output impedance.