Abstract: A fail-safe differential receiver having a differential amplifier adapted to receive first and second differential input signals and generate a differential voltage. A peak detector is coupled to the differential amplifier for generating a detect signal and a comparator is coupled to the peak detector for comparing the detect signal to a threshold voltage and providing a comparison signal. A directing circuit is coupled to the differential amplifier for receiving the first and second differential input signals and is coupled to the comparator for receiving the comparison signal. An output amplifier is coupled to the directing circuit. The directing circuit selectively directs the first and second differential input signals to the output amplifier as a function of the value of the comparison signal from the comparator.

Abstract: A fail-safe differential receiver having a differential amplifier adapted to receive first and second differential input signals and generate a differential voltage. A peak detector is coupled to the differential amplifier for generating a detect signal and a comparator is coupled to the peak detector for comparing the detect signal to a threshold voltage and providing a comparison signal. A directing circuit is coupled to the differential amplifier for receiving the first and second differential input signals and is coupled to the comparator for receiving the comparison signal. An output amplifier is coupled to the directing circuit. The directing circuit selectively directs the first and second differential input signals to the output amplifier as a function of the value of the comparison signal from the comparator.

Abstract: A multiplexer circuit for selecting one of first and second input signals based on a first input select signal includes a multiplexer, a control circuit and an enable buffer. The multiplexer selects one of the first and second input signals based on a second input select signal generated by the control circuit and provides a second output signal. The control circuit receives the second output signal and the first input select signal to generate the second input select signal and an enable signal where the signals have transitions synchronized to the transitions of the second output signal. The enable buffer operates to allow or disallow the second output signal to be passed as the output signal of the multiplexer circuit in response to the enable signal. The multiplexer circuit operates to eliminate runt pulse generation during the switching over of the input signals to provide an error-free output data stream.

Abstract: A multiplexer circuit for selecting one of first and second input signals based on a first input select signal includes a multiplexer, a control circuit and an enable buffer. The multiplexer selects one of the first and second input signals based on a second input select signal generated by the control circuit and provides a second output signal. The control circuit receives the second output signal and the first input select signal to generate the second input select signal and an enable signal where the signals have transitions synchronized to the transitions of the second output signal. The enable buffer operates to allow or disallow the second output signal to be passed as the output signal of the multiplexer circuit in response to the enable signal. The multiplexer circuit operates to eliminate runt pulse generation during the switching over of the input signals to provide an error-free output data stream.