Patents by Inventor Uwe Brandt
Uwe Brandt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11313366Abstract: The application relates to a device for conveying a medium having a working machine (2) and multiple carrier shafts (25, 35) with transport elements (22, 32) for the medium to be conveyed arranged on them, along a drive (3) that sets the carrier shafts (25, 35) in rotation, wherein the drive (3) has multiple driven shafts (20, 30), each of which is coupled with not less than one carrier shaft (25, 35).Type: GrantFiled: November 19, 2015Date of Patent: April 26, 2022Assignee: ITT BORNEMANN GmbHInventors: Jens-Uwe Brandt, Marco Bredemeier, Joerg Lewerenz
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Patent number: 11143180Abstract: The invention concerns a method and an apparatus for operating a multi-phase pump which has a suction-side inlet (10) and a discharge-side outlet (20) and which pumps a multi-phase mixture charged with solids, comprising the following steps: a. pumping a multi-phase mixture into a discharge-side separation chamber (45), b. separating a gaseous phase from a liquid phase and a solid phase in the separation chamber (45), c. separating the liquid phase from the solid phase in the separation chamber (45), and d. supplying a portion of the liquid phase freed from the solid phase to the suction side.Type: GrantFiled: May 23, 2017Date of Patent: October 12, 2021Assignee: ITT Bornemann GmbHInventors: Gerhard Rohlfing, Jens-Uwe Brandt
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Patent number: 11036647Abstract: A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.Type: GrantFiled: June 7, 2019Date of Patent: June 15, 2021Assignee: International Business Machines CorporationInventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Köhler, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski
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Patent number: 10956341Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.Type: GrantFiled: January 27, 2020Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert
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Patent number: 10929312Abstract: Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the techniques include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. The techniques also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. The techniques include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.Type: GrantFiled: May 7, 2019Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro
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Publication number: 20200224657Abstract: The application relates to a system for conveying a medium having not less than two working machines (2, 2a, 2b, 2c) that each have not less than one carrier shaft (25, 35) with transport elements (22, 32) for the medium to be conveyed arranged on them, and not less than one drive (3, 3a, 3b, 3c) that sets the respective carrier shaft (25, 35) in rotation, with multiple working machines (2, 2a, 2b, 2c) connected in series, so that the medium is conveyed to a working machine (2, 2a, 2b, 2c) arranged downstream, and so that a separate drive (3, 3a, 3b, 3c) is assigned to each of the working machines (2, 2a, 2b, 2c) and that the drives (3, 3a, 3b, 3c) are connected in parallel with each other and connected to a common power supply system (5).Type: ApplicationFiled: March 16, 2020Publication date: July 16, 2020Applicant: ITT Bornemann GmbHInventors: JENS-UWE BRANDT, JOERG LEWERENZ, MARCO BREDEMEIER
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Patent number: 10698835Abstract: A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.Type: GrantFiled: December 28, 2017Date of Patent: June 30, 2020Assignee: International Business Machines CorporationInventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Köhler, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski
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Publication number: 20200159670Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.Type: ApplicationFiled: January 27, 2020Publication date: May 21, 2020Inventors: Uwe BRANDT, Markus HELMS, Christian JACOBI, Markus KALTENBACH, Thomas KOEHLER, Frank LEHNERT
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Patent number: 10635603Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.Type: GrantFiled: April 8, 2019Date of Patent: April 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert
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Patent number: 10621105Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.Type: GrantFiled: April 8, 2019Date of Patent: April 14, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert
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Patent number: 10590930Abstract: The application relates to a system for conveying a medium having not less than two working machines (2, 2a, 2b, 2c) that each have not less than one carrier shaft (25, 35) with transport elements (22, 32) for the medium to be conveyed arranged on them, and not less than one drive (3, 3a, 3b, 3c) that sets the respective carrier shaft (25, 35) in rotation, with multiple working machines (2, 2a, 2b, 2c) connected in series, so that the medium is conveyed to a working machine (2, 2a, 2b, 2c) arranged downstream, and so that a separate drive (3, 3a, 3b, 3c) is assigned to each of the working machines (2, 2a, 2b, 2c) and that the drives (3, 3a, 3b, 3c) are connected in parallel with each other and connected to a common power supply system (5).Type: GrantFiled: November 19, 2015Date of Patent: March 17, 2020Assignee: ITT Bornemann GmbHInventors: Jens-Uwe Brandt, Joerg Lewerenz, Marco Bredemeier
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Publication number: 20190286573Abstract: A method for operating translation look-aside buffers, TLBs, in a multiprocessor system. A purge request is received for purging one or more entries in the TLB. When the thread doesn't require access to the entries to be purged the execution of the purge request at the TLB may start. When an address translation request is rejected due to the TLB purge, a suspension time window may be set. During the suspension time window, the execution of the purge is suspended and address translation requests of the thread are executed. After the suspension window is ended the purge execution may be resumed. When the thread requires access to the entries to be purged, it may be blocked for preventing the thread sending address translation requests to the TLB and upon ending the purge request execution, the thread may be unblocked and the address translation requests may be executed.Type: ApplicationFiled: June 7, 2019Publication date: September 19, 2019Inventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Köhler, Frank Lehnert, Jennifer A. Navarro, Rebecca S. Wisniewski
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Publication number: 20190258588Abstract: Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the techniques include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. The techniques also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. The techniques include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.Type: ApplicationFiled: May 7, 2019Publication date: August 22, 2019Inventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro
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Patent number: 10387326Abstract: A computer-implemented method includes associating an initial use order with a plurality of target sets of a translation lookaside buffer (TLB), where the initial use order indicates an order of use of the plurality of target sets. The plurality of target sets are associated with an initial least-recently-used (LRU) state based on the initial use order. A new use order for the plurality of target sets is generated. Generating the new use order includes moving a first target set to a least-recently-used position, responsive to a purge of the first target set. The LRU state of the plurality of target sets is updated based on the new use order, responsive to the purge of the first target set. The first target set is identified as eligible for replacement according to an LRU replacement policy of the TLB, based at least in part on the purge of the first target set.Type: GrantFiled: November 14, 2017Date of Patent: August 20, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Markus Helms, Thomas Köhler, Frank Lehnert
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Patent number: 10380032Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.Type: GrantFiled: March 9, 2017Date of Patent: August 13, 2019Assignee: INTERNATINOAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert
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Patent number: 10380033Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.Type: GrantFiled: October 31, 2017Date of Patent: August 13, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert
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Publication number: 20190236025Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.Type: ApplicationFiled: April 8, 2019Publication date: August 1, 2019Inventors: Uwe BRANDT, Markus HELMS, Christian JACOBI, Markus KALTENBACH, Thomas KOEHLER, Frank LEHNERT
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Publication number: 20190236024Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.Type: ApplicationFiled: April 8, 2019Publication date: August 1, 2019Inventors: Uwe BRANDT, Markus HELMS, Christian JACOBI, Markus KALTENBACH, Thomas KOEHLER, Frank LEHNERT
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Patent number: 10353827Abstract: Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the embodiments include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. Embodiments also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. Embodiments include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.Type: GrantFiled: June 7, 2017Date of Patent: July 16, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro
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Patent number: 10353828Abstract: Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the embodiments include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. Embodiments also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. Embodiments include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.Type: GrantFiled: November 13, 2017Date of Patent: July 16, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro